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ST72F324J Datasheet(PDF) 99 Page - STMicroelectronics

Part # ST72F324J
Description  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F324J Datasheet(HTML) 99 Page - STMicroelectronics

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 54).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 54).
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 00 xx xxxx (xxh)
Bits 7:6= SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 5:3 = SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Bits 2:0 = SCR[2:0]
SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
70
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
PR Prescaling factor
SCP1
SCP0
10
0
30
1
41
0
13
1
1
TR dividing factor
SCT2
SCT1
SCT0
1
000
2
001
4
010
8
011
16
100
32
101
64
110
128
1
1
1
RR Dividing factor
SCR2
SCR1
SCR0
1
000
2
001
4
010
8
011
16
100
32
101
64
110
128
1
1
1


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