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PALC22V10B Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. PALC22V10B
Description  Reprogrammable CMOS PAL Device
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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PALC22V10B Datasheet(HTML) 1 Page - Cypress Semiconductor

   
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USE ULTRA37000™ FOR
ALL NEW DESIGNS
Reprogrammable CMOS PAL® Device
PALC22V10B
This is an abbreviated data sheet. Contact a Cypress
representative for complete specifications.
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-03018 Rev. *A
Revised April 22, 2004
Features
• Advanced second generation PAL architecture
•Low power
— 90 mA max. standard
— 100 mA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
— 2 x (8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
— 15 ns commercial and industrial
10 ns tCO
10 ns tS
15 ns tPD
50 MHz
— 15 ns and “20 ns” military
10/15 ns tCO
10/17 ns tS
15/20 ns tPD
50/31 MHz
• Up to 22 input terms and 10 outputs
• Enhanced test features
— Phantom array
—Top test
— Bottom test
—Preload
• High reliability
— Proven EPROM technology
— 100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, PLCC
available
Functional Description
The Cypress PALC22V10B is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new
concept, the “Programmable Macrocell.”
The PALC22V10B is executed in a 24-pin 300-mil molded DIP,
a 300-mil windowed cerDIP, a 28-lead square ceramic
leadless chip carrier, a 28-lead square plastic leaded chip
carrier, and provides up to 22 inputs and 10 outputs. When the
windowed cerDIP is exposed to UV light, the 22V10B is erased
and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually
Logic Block Diagram (PDIP/CDIP)
Macrocell
8
10
12
14
16
16
14
12
10
8
11
10
9
8
76
54
3
2
1
12
13
14
15
16
17
18
19
20
21
22
23
24
Preset
PROGRAMMABLE
ANDARRAY
(132X 44)
II
I
I
II
II
I
I
CP/I
VSS
I
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell


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