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NCP12600ACBSN65T1G Datasheet(PDF) 7 Page - ON Semiconductor |
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NCP12600ACBSN65T1G Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 24 page NCP12600 www.onsemi.com 7 Table 3. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted) Characteristics Unit Max Typ Min Symbol Conditions DRIVE OUTPUT Rise time CDRV = 1 nF, from 10% to 90% tr − 40 ns Fall time CDRV = 1 nF, from 90% to 10% tf − 30 ns DRV Low voltage VCC = VCC(off) + 0.2 V, CDRV = 220 pF, RDRV = 33 kW VDRV(low) 8 − − V DRV High voltage VCC = VCC(OVP)−0.2 V, CDRV = 220 pF, RDRV = 33 kW VDRV(high) 10 12 14 V Source current Peak source current VGS = 0 V Isource 300 mA Sink current Peak sink current VGS = 12 V Isink 500 mA PROTECTIONS Auto−recovery thermal shutdown Device switching TSHTDN − 150 − °C Thermal Shutdown Hysteresis Device switching TSHTDN(HYS) − 40 − °C Fault level detection for OVP, demagnetization pin, toff sensing Internal sample Vout increasing VOVP1 2.85 3.15 3.35 V Fault level detection on CS pin for OTP implemen- tation – confirmation delay is TPP Internal sample VCS increasing VOTP 0.97 1 1.03 V Over Voltage Protection on the Vcc pin – VOVP2 24 25.5 27 V Sampling delay for OTP and OVP detection (Fsw = 65 kHz) Sampling event on ZCD and CS pins Tdelay_ZCD1 1.2 1.5 1.8 ms Sampling delay for OTP and OVP detection (Fsw = 100 kHz) Sampling event on ZCD and CS pins Tdelay_ZCD2 0.8 1.1 1.3 ms Number of drive cycles before latch confirmation on OVP1 and 2 VZCD > VOVP1 Tlatch_count − 8 − − Timer Delay Before Fault Acknowledgment − Condition 1 – single OCP only CS pin is w 0.7 V TPP1 55 64 75 ms Timer Delay Before Fault Acknowledgment in Overload Condition – dual OCP only CS pin w 0.5 V TOCP 200 256 300 ms Timer Delay Before Fault Acknowledgment with dual OCP – dual OCP only CS pin is w 0.7 V TPP2 55 64 75 ms Timer Delay in Clock Cycles Before Fault Acknowledgment when in Output Short Circuit – Condition 2 VZCD < 0.4 V Unit is clock cycles TSCP 8 4. OPP is not active as long as the negative voltage on the ZCD pin during ton is less than –60 mV. 5. beyond 3.8 V, the peak current is clamped to VILIM. 6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Condition 1: VFB is pushed to its maximum open−loop value. The demagnetization pin during the off−time is above 0.4 V. Condition 2: VFB is pushed to its maximum open−loop value. The demagnetization pin during the off−time is less than 0.4 V. 8 clock cycles are counted and the part latches off or goes into auto−recovery. This mechanism only activates once the 5−ms soft−start sequence is completed. |
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