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PTV05020W Datasheet(PDF) 3 Page - Texas Instruments |
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PTV05020W Datasheet(HTML) 3 Page - Texas Instruments |
3 / 17 page www.ti.com ELECTRICAL CHARACTERISTICS PTV05020W SLTS232 – JANUARY 2005 operating at 25 °C free-air temperature, V I = 5 V, VO = 3.3 V, C1 = 680 µF, C2 = 22 µF, C3 = 0 µF, and IO = IO max (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO Output current Natural convection airflow 0 18 (1) A VI Input voltage range Over IO load range 4.5 5.5 V Set-point voltage tolerance ±2% (2) Temperature variation –40 °C < T A < 85°C ±0.5% Line regulation Over VI range ±5 mV VO Load regulation Over IO range ±5 mV Total output variation Includes set-point, line, load, –40 °C ≤ T A≤ 85°C ±3 (2) %Vo Adjust range Over VI range 0.8 3.6 V RSET = 698 Ω, VO = 3.3 V 94% RSET = 2.21 kΩ, VO = 2.5 V 93% RSET = 5.49 kΩ, VO = 1.8 V 90% η Efficiency IO = IO max RSET = 8.87 kΩ, VO = 1.5 V 89% RSET = 17.4 kΩ, VO = 1.2 V 87% RSET = 36.5 kΩ, VO = 1 V 85% Output voltage ripple (pk-pk) 20-MHz bandwidth 20 mVPP IO (trip) Overcurrent threshold Reset, followed by auto-recovery 35 A 1-A/µs load step, 50 to 100% IO max, C3 = 330 µF Transient response Recovery time 70 µs Vo over/undershoot 120 mV IIL Input low current Pin to GND –0.13 mA Track control (pin 9) Control slew-rate limit C3 ≤ C3 (max) 1 V/ms VI increasing 4.3 4.5 UVLO Undervoltage lockout V VI decreasing 3.1 3.7 VIH Input high voltage VI – 0.5 Open (3) Referenced to GND V Inhibit control (pin 12) VIL Input low voltage –0.2 0.6 IIL Input low current Pin to GND –0.24 mA II (stby) Input standby current Inhibit (pin 12) to GND, Track (pin 9) open 10 mA ƒ S Switching frequency Over VI and IO ranges 250 300 340 kHz Nonceramic (C1) 680 (4) External input capacitance µF Ceramic (C2) 22 (4) Nonceramic 0 330 (5) 11,000 (6) Capacitance value µF External output capacitance (C3) Ceramic 0 300 Equivalent series resistance (nonceramic) 4 (7) m Ω Per Telcordia SR-332, 50% stress, TA = 40°C, ground MTBF Reliability 5 106 Hrs benign (1) See thermal derating curves for safe operating area (SOA), or consult factory for appropriate derating. (2) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1%, with 100 ppm/ °C or better temperature stability. (3) This control pin is pulled up to the input voltage, VI. If this input is left open circuit, the module will operate when input power is applied. A small low-leakage (< 100 nA) MOSFET is recommended for control. For further information, consult the related application note. (4) A 22-µF high-frequency ceramic capacitor and 680-µF electrolytic input capacitor are required for proper operation. The electrolytic capacitor must be rated for 750 mArms minimum ripple current. Consult the Application Information for further guidance on capacitor selection. (5) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the transient response. (6) This is the calculated maximum. The minimum ESR limitation often results in a lower value. Consult the Application Information for further guidance. (7) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ω as the minimum when using max-ESR values to calculate. 3 |
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