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K6R4016C1C-C15 Datasheet(PDF) 2 Page - Samsung semiconductor |
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K6R4016C1C-C15 Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 11 page K6R4016C1C-C, K6R4016C1C-E, K6R4016C1C-I CMOS SRAM PRELIMPreliminaryPPPPPPPPPINARY Rev 4.0 - 2 - September 2001 256K x 16 Bit High-Speed CMOS Static RAM The K6R4016C1C is a 4,194,304-bit high-speed Static Ran- dom Access Memory organized as 262,144 words by 16 bits. The K6R4016C1C uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control(UB, LB). The device is fabri- cated using SAMSUNG ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4016C1C is packaged in a 400mil 44-pin plastic SOJ or TSOP(II) forward or 48 Fine pitch BGA. GENERAL DESCRIPTION FEATURES • Fast Access Time 10,12,15ns(Max.) • Low Power Dissipation Standby (TTL) : 60mA(Max.) (CMOS) : 10mA(Max.) Operating K6R4016C1C-10 : 185mA(Max.) K6R4016C1C-12 : 175mA(Max.) K6R4016C1C-15 : 165mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16 • Standard Pin Configuration K6R4016C1C-J : 44-SOJ-400 K6R4016C1C-T : 44-TSOP2-400BF K6R4016C1C-F : 48-Fine pitch BGA with 0.75 Ball pitch Clk Gen. I/O1~I/O8 OE UB CS FUNCTIONAL BLOCK DIAGRAM Data Cont. Column Select CLK Gen. Pre-Charge Circuit Memory Array 1024 Rows 256 x 16 Columns I/O Circuit & I/O9~I/O16 Data Cont. WE LB K6R4016C1C-C10/C12/C15 Commercial Temp. K6R4016C1C-E10/E12/E15 Extended Temp. K6R4016C1C-I10/I12/I15 Industrial Temp. ORDERING INFORMATION A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 |
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