K6R4016C1C-C, K6R4016C1C-E, K6R4016C1C-I

CMOS SRAM

PRELIMPreliminaryPPPPPPPPPINARY

Rev 4.0

- 6 -

September 2001

WRITE CYCLE*

* The above parameters are also guaranteed at extended and industrial temperature range.

Parameter

Symbol

K6R4016C1C-10

K6R4016C1C-12

K6R4016C1C-15

Unit

Min

Max

Min

Max

Min

Max

Write Cycle Time

10

-

12

-

15

-

ns

Chip Select to End of Write

7

-

8

-

10

-

ns

Address Set-up Time

0

-

0

-

0

-

ns

Address Valid to End of Write

7

-

8

-

10

-

ns

Write Pulse Width(OE High)

7

-

8

-

10

-

ns

Write Pulse Width(OE Low)

10

-

12

-

15

-

ns

UB, LB Valid to End of Write

7

-

8

-

10

-

ns

Write Recovery Time

0

-

0

-

0

-

ns

Write to Output High-Z

0

5

0

6

0

7

ns

Data to Write Time Overlap

5

-

6

-

7

-

ns

Data Hold from Write Time

0

-

0

-

0

-

ns

End Write to Output Low-Z

3

-

3

-

3

-

ns

Address

Data Out

Previous Valid Data

Valid Data

TIMING DIAGRAMS