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AD7490BRUZ Datasheet(PDF) 24 Page - Analog Devices |
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AD7490BRUZ Datasheet(HTML) 24 Page - Analog Devices |
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24 / 29 page  Data Sheet AD7490 Rev. D | Page 23 of 28 If the WEAK/TRI bit in the control register is set to 1, instead of returning to true three-state on the 16th SCLK falling edge, the DOUT line is pulled weakly to the logic level corresponding to ADD3 of the next serial transfer. This is done to ensure that the MSB of the next serial transfer is set up in time for the first SCLK falling edge after the CS falling edge. If the WEAK/TRI bit is set to 0 and the DOUT line has been in true three-state between conversions, the ADD3 address bit may not be set up in time for the DSP/microcontroller to clock it in successfully, depending on the particular DSP or microcontroller interfacing to the AD7490. In this case, ADD3 would only be driven from the falling edge of CS and must then be clocked in by the DSP on the following falling edge of SCLK. However, if the WEAK/ TRI bit is set to 1, although DOUT is driven with the ADD3 address bit since the last conversion, it is nevertheless so weakly driven that another device may still take control of the bus. It does not lead to a bus contention (for example, a 10 kΩ pull-up or pull-down resistor is sufficient to overdrive the logic level of ADD3 between conversions), and all 16 channels may be identified. If this does happen and another device takes control of the bus, it is not guaranteed that DOUT will be fully driven to ADD3 again in time for the read operation when control of the bus is taken back. This is especially useful if using an automatic sequence mode to identify to which channel each result corresponds. If only the first eight channels are in use, Address Bit ADD3 does not need to be decoded, and whether it is successfully clocked in as a 1 or 0 does not matter as long as it is still counted by the DSP/ microcontroller as the MSB of the 16-bit serial transfer. POWER vs. THROUGHPUT RATE By operating the AD7490 in auto shutdown or auto standby mode, the average power consumption of the ADC decreases at lower throughput rates. Figure 29 shows that as the throughput rate is reduced, the part remains in shutdown state longer and the average power consumption drops accordingly over time. For example, if the AD7490 is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz (VDD = 5 V), with PM1 = 0 and PM0 = 1 (that is, the device is in auto shutdown mode), the power consumption is calculated as shown in Equation 1. The maximum power dissipation during normal operation is 12.5 mW (VDD = 5 V). If the power-up time from auto shut- down is one dummy cycle, that is, 1 µs, and the remaining conversion time is another cycle, that is, 1 µs, then the AD7490 can be said to dissipate 12.5 mW for 2 µs during each conver- sion cycle. For the remainder of the conversion cycle, 8 µs, the part remains in shutdown mode. The AD7490 can be said to dissipate 2.5 µW for the remaining 8 µs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is mW 502 . 2 μW 5 . 2 10 8 mW 5 . 12 10 2 = × + × (1) When operating the AD7490 in auto standby mode (PM1 = PM0 = 0 at 5 V, 100 kSPS), the AD7490 power dissipation is calculated as shown in Equation 2. The maximum power dissipation is 12.5 mW at 5 V during nor- mal operation. Again the power-up time from auto standby is one dummy cycle, 1 µs, and the remaining conversion time is another dummy cycle, 1 µs. The AD7490 dissipates 12.5 mW for 2 µs during each conversion cycle. For the remainder of the conversion cycle, 8 µs, the part remains in standby mode, dissipating 460 µW for 8 µs. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each conversion cycle is mW 868 . 2 μW 460 10 8 mW 5 . 12 10 2 = × + × (2) Figure 29 shows the power vs. throughput rate when using both the auto shutdown mode and auto standby mode with 5 V supplies. At the lower throughput rates, power consumption for the auto shutdown mode is lower than that for the auto standby mode, with the AD7490 dissipating less power when in shut- down compared to standby. As the throughput rate is increased, however, the part spends less time in power-down states; hence, the difference in power dissipated is negligible between modes. For 3 V supplies, the power consumption of the AD7490 decreases. Similar power calculations can be done at 3 V. 10 0.01 0.1 1 0 50 100 150 200 250 300 350 THROUGHPUT (kSPS) VDD = 5V AUTO STANDBY AUTO SHUTDOWN Figure 29. Power vs. Throughput Rate in Auto Shutdown and Auto Standby Mode |
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