Data Sheet

AD7674

Rev. B | Page 9 of 28

Pin No.

Mnemonic

Type1

Description

11, 12

D4/DIVSCLK[0],

D5/DIVSCLK[1]

DI/O

In all modes except Mode 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. In

Mode 3, serial interface mode, when EXT/INT is low and RDC/SDIN is low (serial master read after

convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial

clock that clocks the data output. In other serial modes, these pins are not used.

13

D6/EXT/INT

DI/O

In all modes except Mode 3, this output is used as Bit 6 of the parallel port data output bus. In Mode 3,

serial interface mode, this input, part of the serial port, is used as a digital select input for choosing the

internal data clock or an external data clock. With EXT/INT tied low, the internal clock is selected on

the SCLK output. With EXT/INT set to a logic high, the output data is synchronized to an external clock

signal connected to the SCLK input.

14

D7/INVSYNC

DI/O

In all modes except Mode 3, this output is used as Bit 7 of the parallel port data output bus. In Mode 3,

serial interface mode, this input, part of the serial port, is used to select the active state of the

SYNC signal. When low, SYNC is active high. When high, SYNC is active low.

15

D8/INVSCLK

DI/O

In all modes except Mode 3, this output is used as Bit 8 of the parallel port data output bus. In Mode 3,

serial interface mode, this input, part of the serial port, is used to invert the SCLK signal. It is active in

both master and slave mode.

16

D9/RDC/SDIN

DI/O

In all modes except Mode 3, this output is used as Bit 9 of the parallel port data output bus. In Mode 3,

serial interface mode, this input, part of the serial port, is used as either an external data input or a

read mode selection input depending on the state of EXT/INT. When EXT/INT is high, RDC/SDIN can be

used as a data input to daisy-chain the conversion results from two or more ADCs onto a single

SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after

the initiation of the read sequence. When EXT/INT is low, RDC/SDIN is used to select the read mode.

When RDC/SDIN is high, the data is output on SDOUT during conversion. When RDC/SDIN is low, the

data can be output on SDOUT only when the conversion is complete.

17

OGND

P

Input/Output Interface Digital Power Ground.

18

OVDD

P

Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should

not exceed DVDD by more than 0.3 V.

19

DVDD

P

Digital Power. Nominally at 5 V.

20

DGND

P

Digital Power Ground.

21

D10/SDOUT

DO

In all modes except Mode 3, this output is used as Bit 10 of the parallel port data output bus. In Mode 3,

serial interface mode, this output, part of the serial port, is used as a serial data output synchronized

to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the conversion

result, MSB first, from its internal shift register. The data format is determined by the logic level of

OB/2C. In serial mode when EXT/INT is low, SDOUT is valid on both edges of SCLK. In serial mode

when EXT/INT is high and INVSCLK is low, SDOUT is updated on the SCLK rising edge and is valid on

the next falling edge; if INVSCLK is high, SDOUT is updated on the SCLK falling edge and is valid on the

next rising edge.

22

D11/SCLK

DI/O

In all modes except Mode 3, this output is used as Bit 11 of the parallel port data output bus. In Mode 3,

serial interface mode, this pin, part of the serial port, is used as a serial data clock input or output,

dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated

depends upon the logic state of the INVSCLK pin.

23

D12/SYNC

DO

In all modes except Mode 3, this output is used as Bit 12 of the parallel port data output bus. In Mode 3,

serial interface mode, this output, part of the serial port, is used as a digital output frame synchronization

for use with the internal data clock (EXT/INT = logic low). When a read sequence is initiated and INVSYNC is

low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is

initiated and INVSYNC is high, SYNC is driven low and remains low while SDOUT output is valid.

24

D13/RDERROR

DO

In all modes except Mode 3, this output is used as Bit 13 of the parallel port data output bus. In

Mode 3, serial interface mode, and when EXT/INT is high, this output, part of the serial port, is used as

an incomplete read error flag. In slave mode, when a data read is started and not complete when the

following conversion is complete, the current data is lost and RDERROR is pulsed high.

25 to

28

D14 to D17

DO

Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the

interface mode.

29

BUSY

DO

Busy Output. Transitions high when a conversion is started. Remains high until the conversion is

complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used

as a data ready clock signal.

30

DGND

P

Must Be Tied to Digital Ground.

31

RD

DI

Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.