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AD7674 Datasheet(PDF) 25 Page - Analog Devices

Part # AD7674
Description  18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7674 Datasheet(HTML) 25 Page - Analog Devices

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AD7674
Data Sheet
Rev. B | Page 24 of 28
SDOUT
SCLK
D1
D0
X
D17
D16
D15
1
2
3
16
17
18
BUSY
INVSCLK = 0
EXT/INT = 1
RD = 0
t35
t36
t37
t31
t32
t16
t3
CS
CNVST
03083-0-043
Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
BUSY
BUSY
AD7674
#2 (UPSTREAM)
AD7674
#1 (DOWNSTREAM)
RDC/SDIN
SDOUT
CNVST
CS
SCLK
RDC/SDIN
SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
03083-0-044
Figure 45. Two AD7674 Devices in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 44 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain feature
in this mode, and the RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been initiated.
MICROPROCESSOR INTERFACING
The AD7674 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7674 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
input/output ports on a microcontroller. A variety of external
buffers can be used with the AD7674 to prevent digital noise
from coupling into the ADC. The Serial Peripheral Interface
(SPI) section illustrates the use of the AD7674 with an SPI
equipped DSP, the ADSP-2191M.
Serial Peripheral Interface (SPI)
The AD7674 digital interface is compatible with SPI. As an
example, Figure 46 shows an interface diagram between the
AD7674 and the SPI equipped ADSP-2191M. To accommodate
the slower speed of the DSP, the AD7674 acts as a slave device,
and data must be read after conversion. This mode also allows
the daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-2191M is configured for master
mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI Control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbps, which allows it to read an ADC result in
about 1.1 µs. When a higher sampling rate is desired, use of one
of the parallel interface modes is recommended.
AD7674*
ADSP-2191M*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
Figure 46. Interfacing the AD7674 to an SPI Interface


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