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AD7674 Datasheet(PDF) 22 Page - Analog Devices |
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AD7674 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 29 page  Data Sheet AD7674 Rev. B | Page 21 of 28 t9 RESET DATA BUS BUSY CNVST t8 03083-0-035 Figure 36. RESET Timing CNVST BUSY DATA BUS CS = RD = 0 PREVIOUS CONVERSION DATA NEW DATA t1 t10 t4 t3 t11 03083-0-036 Figure 37. Master Parallel Data Timing for Reading (Continuous Read) PARALLEL INTERFACE The AD7674 is configured to use the parallel interface with an 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 38 and Figure 39, respectively. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. Refer to Table 7 for a detailed description of the different options available. DATA BUS t12 t13 BUSY CS RD CURRENT CONVERSION 03083-0-037 Figure 38. Slave Parallel Data Timing for Reading (Read After Convert) CS = 0 CNVST, RD t1 PREVIOUS CONVERSION DATA BUS t12 t13 BUSY t4 t3 03083-0-038 Figure 39. Slave Parallel Data Timing for Reading (Read During Convert) CS RD A0, A1 PINS D[15:8] PINS D[7:0] HI-Z HI-Z HIGH BYTE LOW BYTE LOW BYTE HIGH BYTE HI-Z HI-Z t12 t12 t13 03083-0-039 Figure 40. 8-Bit and 16-Bit Parallel Interface SERIAL INTERFACE The AD7674 is configured to use the serial interface when MODE0 and MODE1 are held high. The AD7674 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. MASTER SERIAL INTERFACE Internal Clock The AD7674 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7674 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 41 and Figure 42 show the detailed timing diagrams of these two modes. Usually, because the AD7674 is used with a fast throughput, the master read during conversion mode is the most recommended serial mode. In read during conversion mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In read after conversion mode, note that unlike in other modes, the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. To accommodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. |
Similar Part No. - AD7674_17 |
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Similar Description - AD7674_17 |
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