9

© 2004 IXYS All rights reserved

IXBD4410

IXBD4411

with respect to KG at IM.

When the command arrives to switch

on the Power MOSFET device, the

CMOS switch shorting IM to KG is

turned off. The driven Power MOSFET

device is switched on approximately

100 ns to 1

µs later, and with typical

load conditions, its drain-to-source

potential, V

10

µs of delay to collapse to the normal

on-state voltage level. To prevent false

triggering due to this, C8 or C12 in

parallel combination with R10 and R11,

or R13 and R14, delays the IM input

signal. During this turn-on interval, the

voltage across C8 or C12 will rise until

the Power MOSFET device finally

comes on and pulls the voltage across

C8 or C12 back down. If the MOSFET

device load circuit is shorted, its V

DS

voltage cannot collapse at turn-on. In

this case, the voltage across C8 or C12

rises rapidly until it reaches 300 mV,

tripping the fault flip-flop and shutting

down the driver output. At the same

time, C8 or C12 must be kept small

enough that the added delay does not

slow down the detection of a short

circuit event so much that the Power

MOSFET device fails before the driver

realizes that it is in trouble.

Three Phase Motor Controls

Fig. 8 is a block diagram of a typical 3-

phase PWM voltage-source inverter

Fig. 8: Typical 3-phase motor control system block diagram

motor control. The power circuit

consists of six power switching transis-

tors with freewheeling diodes around

each of them. The control function may

be performed digitally by a microproces-

sor, microcontroller, DSP chip, or user

custom IC; or it may be performed by a

PC board full of random logic and

analog circuits. In any of these cases,

the PWM command for all six power

transistors is generated in one circuit,

and this circuit is usually referred to

system ground potential - the bottom

terminal of the power bridge.

The ISOSMART™ family of drivers is

the interface between the world of

control logic and the world of power, 5 V

input logic commands precisely control

actions at high voltage and current

(1200 V and 100 A in a typical applica-

tion). Fig. 6 is a detailed schematic of

one phase of three 3-phase motor

control, showing the interconnection of

the IXBD4410/4411 and its associated

circuitry.

PCB Layout Considerations

The IXBD4410/4411 is intended to be

used in high voltage, high speed, high

dv/dt applications.

To ensure proper operation, great care

must be taken in laying out the printed

circuit board. The layout critical areas

include the communication links, current

sense, gate drive, and supply bypass-

ing.

The communication path should be as

short as possible. Added inductance

disturbs the frequency response of the

signal path, and these distortions may

cause false triggering in the receiver.

The transformer should be placed

between the two ICs with the orientation

of one IC reversed (Fig. 9).

Capacitance between the high- and low-

side should be minimized. No signal

trace should run underneath the

communication path, and high- and low-

side traces should be separated on the

PCB. The dv/dt of the high-side during

power stage switching may cause false

logic transitions in low-side circuits due

to capacitive coupling.

The low signal pulse transformer

provides the isolation between high-and

low-side circuits. For 460 V~ line

operation, a spacing of 4 mm is recom-

mended between low- and high-side

circuits, and a transformer HIPOT

specification of at least 1500 V~ is

required. This creep spacing is usually

adequate to control leakage currents on

the PCB with up to 1200 V~ applied

after 10 to 15 years of accumulated dust

and particulates in a standard industrial

environment. In other environments, or

at other line voltages, this spacing

should be appropriately modified.

The current sense/desaturation detect

input is noise sensitive. The 300 mV trip

point is referred to the KG (Kelvin

ground) pin, and the applied signal must

be kept as clean as possible, A filter is

recommended, preferably a monolithic

ceramic capacitor placed as close to the

IC as possible directly between IM and

KG. To preserve maximum noise

immunity, the KG pin should first be

connected directly to the LG pin, and the

pair then sent directly to the power

transistor source/emitter terminal, or (if a

desaturation detection circuit is used) to

the bottom of the divider resistor chain.

All supply pins must be bypassed with a

low impedance capacitor (preferably

monolithic ceramic construction) with

minimum lead length. The output driver

stage draws 2 A (typical) currents during

transitions at di/dt values in excess of

100 A/

µs. Supply line inductance will

cause supply and ground bounce on the

chip that can cause problems (logic

oscillations and, in severe cases,

possible latch-up failure) without proper

bypassing. These bypass elements are

in addition to the reservoir capacitors

required for the negative Vee supply and

the high-side bootstrapped supply if

these features are used.

Power Circuit Noise Considerations

In a typical transistor inverter, the output

MOSFET may switch on or off with di/dt

>500 A/

µs. Referring to Fig.10 and

assuming that the MOSFET source

terminal has a one inch path on the PCB

to system ground, a voltage as high as

V = 27 nH • 500 A/

µs = 13.5 V can be

developed.