ISP1181A datasheet(7/70 Pages) PHILIPS | Full-speed Universal Serial Bus peripheral controller

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ISP1181A Datasheet(PDF) 7 Page - NXP Semiconductors

Part #	ISP1181A

Description	Full-speed Universal Serial Bus peripheral controller

Download	70 Pages

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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Philips Semiconductors

ISP1181A

Full-speed USB peripheral controller

Product data

Rev. 05 — 08 December 2004

7 of 70

9397 750 13959

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

DATA5

31

26

I/O

bit 5 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA)

DATA4

32

27

I/O

bit 4 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA)

DATA3

33

28

I/O

bit 3 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA)

DATA2

34

29

I/O

bit 2 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA)

DATA1

35

30

I/O

bit 1 of D[15:0]; bidirectional data line

(slew-rate controlled output, 4 mA)

GND

36

31

-

ground supply

VCC(3.3)

37

32

-

supply voltage (3.0 V to 3.6 V); leave this

pin unconnected when using VCC = 5.0 V

AD0

38

33

I/O

multiplexed bidirectional address and data

line; represents address A0 or bit 0 of

D[15:0] in conjunction with input ALE;

level-sensitive input or slew-rate controlled

output (4 mA)

Address phase: a HIGH-to-LOW transition

on input ALE latches the level on this pin as

address A0 (1 = command, 0 = data)

Data phase: during reading this pin outputs

bit D[0]; during writing the level on this pin is

latched as bit D[0]

A0

39

34

I

address input; selects command (A0 = 1) or

data (A0 = 0); in a multiplexed address/data

bus conﬁguration this pin is not used and

must be tied LOW (connect to GND)

RD

40

35

I

read strobe input

WR

41

36

I

write strobe input

ALE

42

37

I

address latch enable input; a HIGH-to-LOW

transition latches the level on pin AD0 as

address information in a multiplexed

address/data bus conﬁguration; must be

tied LOW (connect to GND) for a separate

address/data bus conﬁguration

CS

43

38

I

chip select input

RESET

44

39

I

reset input (Schmitt trigger); a LOW level

produces an asynchronous reset; connect

to VCC for power-on reset (internal POR

circuit)

CLKOUT

45

40

O

programmable clock output (2 mA)

Table 2:

Pin description…continued

Symbol[1]

Pin

Type

Description

TSSOP48

HVQFN48

Similar Part No. - ISP1181A

Manufacturer	Part #	Datasheet	Description
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Similar Description - ISP1181A

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