©2000 Integrated Device Technology, Inc.

MAY 2000

DSC 3739/6

1

8Kx16

MEMORY

ARRAY

(BANK 3)

MUX

MUX

R/

R/

MAILBOX

INTERRUPT

LOGIC

8Kx16

MEMORY

ARRAY

(BANK 1)

MUX

8Kx16

MEMORY

ARRAY

(BANK 0)

MUX

MUX

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

R/

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

R/

3739 drw 01

BANK

SELECT

MUX

HIGH-SPEED

32K x 16 BANK-SWITCHABLE

DUAL-PORTED SRAM WITH

EXTERNAL BANK SELECTS

Features

x

x

x

x

x

32K x 16 Bank-Switchable Dual-Ported SRAM Architecture

–

Four independent 8K x 16 banks

– 512 Kilobit of memory on chip

x

x

x

x

x

Fast asynchronous address-to-data access time: 15ns

x

x

x

x

x

User-controlled input pins included for bank selects

x

x

x

x

x

Independent port controls with asynchronous address &

data busses

x

x

x

x

x

Four 16-bit mailboxes available to each port for inter-

processor communications; interrupt option

IDT707278S/L

NOTES:

1. The first six address pins for each port serve dual functions. When

serve as mailbox address inputs.

2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for

more details.

Functional Block Diagram

x

x

x

x

x

Interrupt flags with programmable masking

x

x

x

x

x

Dual Chip Enables allow for depth expansion without

external logic

x

x

x

x

x

UB and LB are available for x8 or x16 bus matching

x

x

x

x

x

TTL-compatible, single 5V (±10%) power supply

x

x

x

x

x

Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)