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IDT707278S20PF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT707278S20PF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 16 page 6.42 IDT707278S/L 32K x 16 Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges 8 NOTES: 1 . Bank 0 refers to the first 8Kx16 memory spaces, Bank 1 to the second 8Kx16 memory spaces, Bank 2 to the third 8Kx16 memory spaces, and Bank 3 to the fourth 8Kx16 memory spaces. 'LEFT' indicates the bank is assigned to the left port; 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks may be assigned to either port. 2 . The bank select pin inputs must be set at either VIH or VIL - these inputs are not tri-statable. When changing the bank assignments, accesses of the affected banks must be suspended. Accesses may continue uninterrupted in banks that are not being reallocated. 3 . 'H' = VIH, 'L' = VIL, 'X' = Don't Care. Assigning the Banks via the External Bank Selects TherearefourbankselectpinsavailableontheIDT707278, andeach of these pins is associated with a specific bank within the memory array. The pins are user-controlled inputs: access to a specific bank is assigned toaparticularportbysettingtheinputtotheappropriatelevel.Theprocess ofassigningthebanksisdetailedinTruthTableIV.Onceabankisassigned toaport,theowningporthasfullaccesstoreadandwritewithinthatbank. Theoppositeportisunabletoaccessthatbankuntiltheuserreassignsthe port.Accessbyaporttoabankwhichitdoesnotcontrolwillhavenoeffect Truth Table IV Memory Bank Assignment (CE = VIH)(2,3) Mailbox Interrupts and Interrupt Control Registers If the user chooses the mailbox interrupt function, four mailbox locationsareassignedtoeachport.Thesemail-boxlocationsareexternal to the memory array. The mailboxes are accessed bysetting MBSEL = VIL while holding CE = VIH. The mailboxes are 16 bits wide and controllable by byte: the message isuser-definedsincetheseareaddressableSRAMlocations.Aninterrupt is generated to the opposite port upon writing to the upper byte of any mailbox location. A port can read the message it has just written in order toverifyit: thisread willnotalterthestatusoftheinterruptsenttotheopposite port. Theinterruptedportcancleartheinterruptbyreadingtheupperbyte oftheapplicablemailbox.Thisreadwillnotalterthecontentsofthemailbox. The use of mailboxes to generate interrupts to the opposite port and the reading of mailboxes to clear interrupts is detailed in Truth Table V. Ifdesired,anyofthemailboxinterruptscanbeindependentlymasked viasoftware.MaskingoftheinterruptsourcesisdoneintheMaskRegister. The masks are individual and independent: a port can mask any combinationofinterruptsourceswithnoeffectontheothersources.Each port can modify only its own Mask Register. The use of this register is detailed in Truth Table V. Tworegistersareprovidedtopermitinterpretationofinterrupts:these are the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused theinterrupttobegenerated-thespecificmailboxwrittentobytheopposite port.Theinformationinthisregisterprovidespost-masksignals:interrupt sources that have been masked will not be updated. The Interrupt Status Registergivestheuserthestatusofallbitsthatcouldpotentiallycausean interrupt regardless of whether they have been masked. The use of the Interrupt Cause Register and the Interrupt Status Register is detailed in Truth Table V. if written, and if read unknown values on D0-D15 will be returned. Each port can be assigned as many banks within the array as needed, up to and including all four banks. ThebankselectpininputsmustbesetateitherVIHorVIL-theseinputs arenottri-statable.Whenchangingthebankassignments,accessesofthe affectedbanksmustbesuspended.Accessesmaycontinueuninterrupted in banks that are not being reallocated. BKSEL0 BKSEL1 BKSEL2 BKSEL3 BANK AND DIRECTION(1) H X X X BANK 0 LEFT X H X X BANK 1 LEFT X X H X BANK 2 LEFT X X X H BANK 3 LEFT L X XXBANK 0 RIGHT X L XXBANK 1 RIGHT XX L X BANK 2 RIGHT XX X L BANK 3 RIGHT 3739 tbl 13 |
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