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IDT821064 Datasheet(PDF) 14 Page - Integrated Device Technology |
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IDT821064 Datasheet(HTML) 14 Page - Integrated Device Technology |
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14 / 33 page  14 INDUSTRIAL TEMPERATURE RANGE IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE (after the message data in the FSK-RAM having been sent, the FS bit will be cleared to '0' automatically). 3. The length of the Seizure Signal, Mark Signal and Flag Signal are different in different system, for IDT821064, they can be programmed by Global Command 13,14 and 11 respectively. It should be noted that, the Seizure Length is two times of the value that set in Global Command 13, for example, if the SL[7:0] bits of Global Command 13 is 1(d), it means that the Seizure Length is 2(d). 4. As is described in “Addressing of FSK-RAM”, the FSK-RAM consists of 32 words, and each word consists of 16 bits (2 bytes), so it can contain up to 64 bytes of message at one time. If the message data is longer than 64 bytes, users should write them into the FSK-RAM two or more times according to the length of the message. 5. The “Data length” is the number of bytes that written in the FSK- RAM and need to be sent out. During the transmission of FSK signal, an internal counter will count the number of data bytes that transmitted, once it reaches the Data length, the FSK transmission is completed and the FS bit is set to '0'. 6. Because there is only one FSK-RAM shared by four channels of IDT821064, the FSK signal can only generate on one channel at one time, the channel selection is done by the FCS[2:0] bits of Global Command 15. 7. The FSK signal generated by the IDT821064 follows the BELL 202 and CCITT V.23 specifications. Users can select BT or Bellcore standard by setting the BT/Bellcore Select bit (BS) in Global Command 15. The difference between BT and Bellcore is shown in Table 3. 8. The “Mark After Send” bit (MAS) is useful if the total message data is longer than 64 bytes. If the MAS is set to '1', then after sending one frame of FSK-RAM message(=< 64 bytes), IDT821064 will keep sending a series of '1' to hold the communication channel for sending next frame of FSK message, and at the same time, users can update the FSK- RAM with new data. This series of '1' will stop by set the MAS bit to '0' or set the FO bit to '0'. 9. It should be noted that, when writing/reading message data to/from the FSK-RAM via GCI interface, the sequence of read/write is MSB first; but the FSK generator will send these signal (message data) out through channel port with LSB first. Refer to the IDT821064 Application Note for more information. LEVEL METERING The IDT821064 has a level meter which can be shared by all 4 signal channels. The level meter is designed to emulate the off-chip PCM test equipment so as to facilitate the line-card, subscriber line and user telephone set monitoring. The level meter tests the returned signal and reports the measurement result via MPI interface. When combined with Tone Generation and Loopback modes, this allows the microprocessor to test channel integrity. CS[1:0] bits in Global Command 19 select the channel, signal on which will be metered. Level Metering function is enabled by setting LMO bit to ‘1’ in Global Command 19. There is a Level Meter Counter register for this function. It can be accessed by Global Command 18. This register is used to configure the number of time cycles for sampling PCM data (8 kHz sampling rate). The output of Level Metering will be sent to Level Meter Result Low and Level Meter Result High registers (Global Command 16 and 17). The LVLL register contains the lower 7 bits of the output and a data-ready bit (LVLL[0]), while the LVLH register contains the higher 8 bits of the output. An internal accumulator sums the rectified samples until the number configured by Level Meter Counter register is reached. By then, the LVLL[0] bit is set to ‘1’ and accumulation result is latched into the LVLL and LVLH registers simultaneously. Once the LVLH register is read, the LVLL[0] bit will be reset. The LVLL[0] bit will be set high again by a new data available. The contents in LVLL and LVLH will be overwritten by later metering result if they are not read out yet. In Level Metering result read operation, it is highly recommended to read LVLL first. L/C bit in Global Command 19 determines the mode of Level Meter operation. When L/C bit is ‘1’, the Level Meter will measure the linear PCM data, and if LVLL[0] bit is ‘1’ , the measure result will be output to LVLH and LVLL. When L/C bit is ‘0’, compressed PCM will be output transparently to LVLH. The calculation and method of level metering will be described in the Application Note. CHANNEL POWER DOWN/STANDBY MODE Each individual channel of IDT821064 can be powered down independently by Local Command 9. When the channel is powered down (enters into standby mode), The transmission and reception of PCM data, D/A and A/D converters are disabled. In this way, power consumption of the device can be reduced. When IDT821064 is powered up or reset, all four channels will be powered down. All circuits that contain programmed information retain their data when powered down. MPI (Microprocessor Interface) is always active so that new command could be received and executed. POWER DOWN PLL/SUSPEND MODE A suspend mode is offered to the whole chip to save power. In this mode, the PLL block is turned off and DSP operation is disabled. This mode saves much more power consumption than standby mode. In this mode, only Global Command and Local Command can be executed. RAM operation is disabled as internal clock has been turned off. The PLL blocks can be powered down by Global Command 20. Suspend mode can be entered by powering down PLL and all channels. Table 3 - BT/Bellcore Standard of FSK Signal Item BT Bellcore Mark( 1 ) frequency 1300 Hz ± 1.5% 1200Hz ± 1.1% Space ( 0 ) frequency 2100 Hz ± 1.1% 2200 Hz ± 1.1% Transmission rate 1200 baud ± 1% 1200 baud ± 1 % Word format 1 start bit which is ‘0’, 8 word bits (with least significant bit LSB first), 1 stop bit which is ‘1’ 1 start bit which is ‘0’ 8 word bits (with least significant bit LSB first) 1 stop bit which is ‘1’ |
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