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AD7278BUJZ-500RL7 Datasheet(PDF) 17 Page - Analog Devices |
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AD7278BUJZ-500RL7 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 28 page  Data Sheet AD7276/AD7277/AD7278 Rev. D | Page 17 of 28 The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which results in an error of 50 ppm (150 µV) for the 5 mA drawn from it. When VDD = 3 V from the REF193, it corresponds to an error of 0.204 LSB, 0.051 LSB, and 0.0128 LSB for the AD7276, AD7277, and AD7278, respectively. For applications where power consumption is of concern, use the power-down mode of the ADC and the sleep mode of the REF193 reference to improve power performance. See the Modes of Operation section. AD7276/ AD7277/ AD7278 VDD VIN SERIAL INTERFACE 0V TO VDD INPUT DSP/ µC/µP GND SCLK CS SDATA 0.1µF 10µF 1µF TANT 0.1µF 680nF 3V 5V SUPPLY REF193 Figure 22. REF193 as Power Supply to the AD7276/AD7277/AD7278 Table 8 provides typical performance data with various references used as a VDD source with the same setup conditions. Table 8. AD7276 Performance (Various Voltage References IC) Reference Tied to VDD SNR Performance, 1 MHz Input AD780 @ 3 V 71.3 dB AD780 @ 2.5 V 70.1 dB REF193 70.9 dB Analog Input Figure 23 shows an equivalent circuit of the analog input structure of the AD7276/AD7277/AD7278. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward biased and to start conducting current into the substrate. These diodes can conduct a maximum current of 10 mA without causing irreversible damage to the part. Capacitor C1 in Figure 23 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 75 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 4 pF typically when in hold mode and 32 pF typically when in track mode. For ac applications, removing high frequency components from the analog input signal is recommended by using a band-pass filter on the relevant analog input pin. In applications where the harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of these ADCs and can necessitate the use of an input buffer amplifier. The AD8021 op amp is compatible with these devices; however, the choice of the op amp is a function of the particular application. C1 4pF C2 R1 CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED D1 D2 VDD VIN Figure 23. Equivalent Analog Input Circuit When no amplifier is used to drive the analog input, the source impedance should be limited to a low value. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and per- formance degrades. Figure 16 shows a graph of the THD vs. the analog input frequency for different source impedances when using a supply voltage of 3 V and sampling at a rate of 3 MSPS. Digital Inputs The digital inputs applied to the AD7276/AD7277/AD7278 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied to the AD7276/AD7277/ AD7278 can be 6 V and are not restricted by the VDD + 0.3 V limit of the analog inputs. For example, if the AD7276/AD7277/ AD7278 are operated with a VDD of 3 V, then 5 V logic levels can be used on the digital inputs. However, it is important to note that the data output on SDATA still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. For example, unlike with the analog inputs, with the digital inputs, if CS or SCLK is applied before VDD, there is no risk of latch-up. |
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