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DS3143 Datasheet(PDF) 5 Page - Dallas Semiconductor |
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DS3143 Datasheet(HTML) 5 Page - Dallas Semiconductor |
5 / 88 page DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 5 of 88 LIST OF TABLES Table 4-A. Applicable Telecommunications Standards ............................................................................ 8 Table 6-A. Register Map........................................................................................................................ 15 Table 6-B. Status Register Set Example................................................................................................ 17 Table 7-A. BERT/Loopback Interaction—Payload Bits .......................................................................... 20 Table 7-B. BERT/Loopback Interaction—Overhead Bits........................................................................ 21 Table 7-C. Common Line Interface Register Map.................................................................................. 22 Table 7-D. DS3/E3 Framer Register Map .............................................................................................. 32 Table 7-E. DS3 Alarm Criteria ............................................................................................................... 40 Table 7-F. E3 Alarm Criteria .................................................................................................................. 40 Table 7-G. BERT Register Map............................................................................................................. 45 Table 7-H. HDLC Register Map............................................................................................................. 54 Table 7-I. FEAC Register Map............................................................................................................... 63 Table 9-A. JTAG Instruction Codes ....................................................................................................... 71 Table 9-B. JTAG ID Code...................................................................................................................... 72 Table 10-A. Recommended DC Operating Conditions........................................................................... 73 Table 10-B. DC Electrical Characteristics .............................................................................................. 73 Table 11-A. Data Path Timing ............................................................................................................... 74 Table 11-B. Line Loopback Timing ........................................................................................................ 74 Table 11-C. Microprocessor Interface Timing ........................................................................................ 76 Table 11-D. JTAG Interface Timing ....................................................................................................... 81 Table 12-A. Pin Assignments (Sorted by Signal Name)......................................................................... 82 Table 14-A. Thermal Properties, Natural Convection............................................................................. 88 Table 14-B. Theta-JA ( qJA) vs. Airflow.................................................................................................... 88 |
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