ADS5542

SBAS308A − MAY 2004 − REVISED MARCH 2005

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8

t

SLOADS

t

WSCLK

t

OS

t

OH

t

WSCLK

t

SCLK

16 x M

MSB

LSB

LSB

MSB

t

SLOADH

SCLK

SEN

SDATA

Figure 4. Serial Programming Interface Timing Diagram

Table 1. Serial Programming Interface Timing Characteristics

SYMBOL

PARAMETER

MIN(1)

TYP(1)

MAX(1)

UNIT

SCLK Period

50

ns

SCLK Duty Cycle

25

50

75

%

SEN to SCLK setup time

8

ns

SCLK to SEN hold time

6

ns

Data Setup Time

8

ns

Data Hold Time

6

ns

(1) Typ, min, and max values are characterized, but not production tested.

Table 2. Serial Register Table

A3

A2

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DESCRIPTION

1

1

1

0

0

TP<1>

TP<0>

0

0

0

0

0

0

0

0

0

TP<1:0> − Test modes for output data capture

TP<1:0> = 00: Normal mode of operation

TP<1:0> = 01: All outputs forced to 0

TP<1:0> = 10: All outputs forced to 1

TP<1:0> = 11: Each output bit toggles between 0 and

1. There is no ensured relationship between the bits

See Note 2

1

1

1

1

PDN

0

0

0

0

0

0

0

0

0

0

0

PDN = 0 : Normal mode of operation, PDN = 1 :

Device is put in power down (low current) mode

(1) All register contents default to zero on reset.

(2) The patterns given are applicable to the straight offset binary output format. If 2’s complement output format is selected, the test mode outputs

will be the 2’s complement equivalent of these patterns.

Table 3. DATA FORMAT SELECT (DFS TABLE)

DFS-PIN VOLTAGE (VDFS)

DATA FORMAT

CLOCK OUTPUT POLARITY

V

2

12

AV

DD

Straight Binary

Data valid on rising edge

4

12

AV

5

12

AV

DD

2’s Complement

Data valid on rising edge

7

12

AV

8

12

AV

DD

Straight Binary

Data valid on falling edge

V

10

12

AV

DD

2’s Complement

Data valid on falling edge