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CD54HCT640F3A Datasheet(PDF) 1 Page - Texas Instruments

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Part No. CD54HCT640F3A
Description  High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD54HCT640F3A Datasheet(HTML) 1 Page - Texas Instruments

 
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Data sheet acquired from Harris Semiconductor
SCHS192B
Features
• Buffered Inputs
• Three-State Outputs
• Applications in Multiple-Data-Bus Architecture
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD54HC640, CD54HCT640
(CERDIP)
CD74HC640, CD74HCT640
(PDIP, SOIC)
TOP VIEW
Description
The ’HC640 and ’HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
for two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
circuits, and have speeds comparable to low power Schottky
TTL circuits. They can drive 15 LSTTL loads. The ’HC640
and ’HCT640 are inverting buffers.
The direction of data flow (A to B, B to A) is controlled by the
DIR input.
Outputs are enabled by a low on the Output Enable input
(OE); a high OE puts these devices in the high impedance
mode.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DIR
A0
A1
A2
A3
A4
A6
A5
A7
GND
VCC
B0
B1
B2
OE
B3
B4
B5
B6
B7
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC640F3A
-55 to 125
20 Ld CERDIP
CD54HCT640F3A
-55 to 125
20 Ld CERDIP
CD74HC640E
-55 to 125
20 Ld PDIP
CD74HC640M
-55 to 125
20 Ld SOIC
CD74HCT640E
-55 to 125
20 Ld PDIP
CD74HCT640M
-55 to 125
20 Ld SOIC
January 1998 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC640, CD74HC640,
CD54HCT640, CD74HCT640
High-Speed CMOS Logic
Octal Three-State Bus Transceiver, Inverting
[ /Title
(CD74
HC640
,
CD74
HCT64
0)
/Sub-
ject
(High
Speed
CMOS


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