AD5040/5060

Preliminary Technical Data

Rev. PrC | Page 14 of 17

The bias generator, the output amplifier, the DAC and other

associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

DAC register are unaffected when in power-down. The time to

exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for

VDD = 3 V. See Figure 18 for a plot.

MICROPROCESSOR INTERFACING

AD5040/AD5060 to ADSP-2101/ADSP-2103

Interface

Figure 25 shows a serial interface between the AD5040/AD5060

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103

should be set up to operate in the SPORT Transmit Alternate

Framing Mode. The ADSP-2101/ADSP-2103 SPORT is

programmed through the SPORT control register and should

be configured as follows: Internal Clock Operation, Active Low

Framing, 16-Bit Word Length. Transmission is initiated by

writing a word to the Tx register after the SPORT has

been enabled.

Figure 25. AD5040/AD5060 to ADSP-2101/ADSP-2103

Interface

DB23

DB0

SCLK

SYNC

DIN

DB23

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

INVALID WRITE SEQUENCE:

Figure 23. SYNC Interrupt Facility for AD5060.

AD5040/AD5060 to 68HC11/68L11 Interface

Figure 26 shows a serial interface between the AD5060 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5060, while the MOSI

output drives the serial data line of the DAC. The SYNC

signal is derived from a port line (PC7). The setup conditions

for correct operation of this interface are as follows: the

68HC11/68L11 should be configured so that its CPOL bit is a 0

and its CPHA bit is a 1. When data is being transmitted

to the DAC, the SYNC line is taken low (PC7). When the

68HC11/68L11 is configured as above, data appearing on the

MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. In order to load data to the

AD5040/AD5060, PC7 is left low after the first eight bits are

transferred, and a second serial write operation is performed to

the DAC and PC7 is taken high at the end of this procedure.

Figure 26. AD5040/AD5060 to 68HC11/68L11 Interface

AD5040/AD5060 to Blackfin ADSP-BF53X

Interface

Figure 2X shows a serial interface between the AD5641 and the

Blackfin ADSP-53X microprocessor. The ADSP-BF53X processor

family incorporates two dual-channel synchronous serial ports,

SPORT1 and SPORT0 for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5062/63, the

setup for the interface is as follows. DT0PRI drives the SDIN pin of

the AD5062/63, while TSCLK0 drives the SCLK of the part. The

SYNC is driven from TFS0.

Figure 2X. AD5040/AD5060 to Blackfin ADSP-BF53X

Interface

AD5040/AD5060 to 80C51/80L51 Interface

Figure 27 shows a serial interface between the AD5040/AD5060

and the 80C51/80L51 microcontroller. The setup for the

interface is as follows:TXDofthe80C51/80L51drivesSCLKofthe

AD5040/AD5060, while RXD drives the serial data line of the

part. The SYNC signal is again derived from a bit

programmable pin on the port. In this case port line P3.3 is