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MT9V032 Datasheet(PDF) 33 Page - ON Semiconductor |
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MT9V032 Datasheet(HTML) 33 Page - ON Semiconductor |
33 / 61 page MT9V032 www.onsemi.com 33 After integration is stopped, the user provides STLN_OUT pulses to trigger row readout. A full row of data is read out with each STLN_OUT pulse. The user must provide enough time between successive STLN_OUT pulses to allow the complete readout of one row. It is also important to provide additional STLN_OUT pulses to allow the sensors to read the vertical blanking rows. It is recommended that the user program the vertical blank register (R0x06) with a value of 4, and achieve additional vertical blanking between frames by delaying the application of the STFRM_OUT pulse. The elapsed time between the rising edge of STLN_OUT and the first valid pixel data is [horizontal blanking register (R0x05) + 4] clock cycles. Figure 18. Slave Mode Operation Exposure STFRM_OUT LED_OUT STLN_OUT LINE_VALID (input) (input) (input) (output) (output) 1−row time 1−row time 98 master clocks 2 master clocks Vertical Blanking (def=45 lines) Integration Time Signal Path The MT9V032 signal path consists of a programmable gain, a programmable analog offset, and a 10−bit ADC. See “Black Level Calibration” for the programmable offset operation description. Figure 19. Signal Path Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) Gain Selection (R0x35 or result of AGC) ADC Data (9:0) 10 (12) bit ADC C1 C2 + Σ × |
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