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MT9V024 Datasheet(PDF) 34 Page - ON Semiconductor |
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MT9V024 Datasheet(HTML) 34 Page - ON Semiconductor |
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34 / 40 page  MT9V024/D www.onsemi.com 34 Table 20. TWO−WIRE SERIAL BUS CHARACTERISTICS (VPWR = 3.3V +0.3V; TA = Ambient = 25°C) Parameter Symbol Standard−Mode Fast−Mode Unit Min Max Min Max SCLK Clock Frequency fSCL 0 100 0 400 kHz After this period, the first clock pulse is generated tHD;STA 4.0 − 0.6 − ms LOW period of the SCLK clock tLOW 4.7 − 1.3 − ms HIGH period of the SCLK clock tHIGH 4.0 − 0.6 − ms Set-up time for a repeated START condition tSU;STA 4.7 − 0.6 − ms Data hold time tHD;DAT 0 (Note 11) 3.45 (Note 12) 0 (Note 13) 0.9 (Note 12) ms Data set-up time tSU;DAT 250 − 100 (Note 13) − ns Rise time of both SDATA and SCLK signals tr − 1000 20 + 0.1Cb (Note 14) 300 ns Fall time of both SDATA and SCLK signals tf − 300 20 + 0.1Cb (Note 14) 300 ns Set-up time for STOP condition tSU;STO 4.0 − 0.6 − ms Bus free time between a STOP and START condition tBUF 4.7 − 1.3 − ms Capacitive load for each bus line Cb − 400 − 400 pF Serial interface input pin capacitance CIN_SI − 3.3 − 3.3 pF SDATA max load capacitance CLOAD_SD − 30 − 30 pF SDATA pull−up resistor RSD 1.5 4.7 1.5 4.7 kW 8. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 9. Two-wire control is I2C-compatible. 10.All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. 11. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 12.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 13.A Fast-mode I2C-bus device can be used in a Standard-mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard−mode I2C−bus specification) before the SCLK line is released. 14.Cb = total capacitance of one bus line in pF. Minimum Master Clock Cycles In addition to the AC timing requirements described in Table 17, the two−wire serial bus operation also requires certain minimum master clock cycles between transitions. These are specified in Figures 41 through 46, in units of master clock cycles. Figure 41. Serial Host Interface Start Condition Timing SCLK SDATA 4 4 |
Similar Part No. - MT9V024_17 |
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Similar Description - MT9V024_17 |
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