AD7982_17 datasheet(25/26 Pages) AD | 18-Bit, 1 MSPS PulSAR 7 mW ADC in MSOP/LFCSP

25 / 26 page

AD7982

Data Sheet

Rev. D | Page 24 of 25

APPLICATIONS INFORMATION

LAYOUT

The printed circuit board (PCB) that houses the AD7982 must

be designed so the analog and digital sections are separated and

confined to certain areas of the PCB. The pin configuration of

the AD7982, with its analog signals on the left side and its digital

signals on the right side, eases the task of separating the analog

and digital circuitry on a PCB.

Avoid running digital lines under the device; these couple noise

onto the die, unless a ground plane under the AD7982 is used

as a shield. Fast switching signals, such as CNV or clocks, must

not run near analog signal paths. Crossover of digital and

analog signals must be avoided.

It is recommended to use at least one ground plane. It can be

common or split between the digital and analog sections. In the

latter case, the planes must be joined underneath the AD7982

devices.

The AD7982 voltage reference input REF has a dynamic input

impedance and must be decoupled with minimal parasitic

inductances. Decoupling is done by placing the reference

decoupling ceramic capacitor close to, ideally right up against,

the REF and GND pins and connecting themwith wide, low

impedance traces.

Finally, decouple the power supplies of the AD7982, VDD and

VIO, with ceramic capacitors, typically 100 nF, placed close to

the AD7982 and connected using short, wide traces to provide

low impedance paths and to reduce the effect of glitches on the

power supply lines.

An example of layout following these rules is shown in Figure 41

and Figure 42.

EVALUATING THE PERFORMANCE OF THE AD7982

Other recommended layouts for the AD7982 are outlined in the

UG-340 user guide for the EVAL-AD7982SDZ. The evaluation

board package includes a fully assembled and tested evaluation

board, the user guide, and software for controlling the

evaluation board from a PC via the EVAL-SDP-CB1Z.

AD7982

Figure 41. Example Layout of the AD7982 (Top Layer)

Figure 42. Example Layout of the AD7982 (Bottom Layer)

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