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AD7982 Datasheet(PDF) 17 Page - Analog Devices

Part No. AD7982
Description  18-Bit, 1 MSPS PulSAR 7 mW ADC in MSOP/LFCSP
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7982 Datasheet(HTML) 17 Page - Analog Devices

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AD7982
Data Sheet
Rev. D | Page 16 of 25
SINGLE-ENDED TO DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended to differential
driver allows a differential input to the device. The circuit
diagram is shown in Figure 26.
R1 and R2 set the attenuation ratio between the input range and
the ADC voltage range (VREF). R1, R2, and CF are chosen
depending on the desired input resistance, signal bandwidth,
antialiasing, and noise contribution. For example, for the ±10 V
range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. Ensure the
common mode is close to VREF/2. For example, for the ±10 V
range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 =
10.5 kΩ, and R6 = 9.76 kΩ.
20Ω
20Ω
10µF
R1
100nF
+2.5V
+5V REF
+5.2V
–0.2V
CF
R2
R4
R6
±10V,
±5V, ..
R3
R5
REF
VDD
GND
IN+
IN–
AD7982
2.7nF
2.7nF
ADA4941-1
IN
FB
OUTP
OUTN
REF
100nF
Figure 26. Single-Ended to Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7982 voltage reference input, REF, has a dynamic input
impedance and must be driven by a low impedance source with
efficient decoupling between the REF and GND pins, as
explained in the Layout section.
When REF is driven by a very low impedance source (for example,
a reference buffer using the AD8031 or the ADA4807-1), a 10 μF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If using an unbuffered reference voltage, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR435 reference.
If desired, use a reference decoupling capacitor with values as
small as 2.2 μF with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7982 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.5 V. To reduce the
number of supplies needed, tie VIO and VDD together. The
AD7982 is independent of power supply sequencing between VIO
and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 27.
95
90
85
80
75
70
65
60
1
10
100
1000
FREQUENCY (kHz)
Figure 27. PSRR vs. Frequency
The AD7982 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the
sampling rate. The power scaling linearly with throughput makes
the device ideal for low sampling rates (even of a few hertz) and low
battery-powered applications.
10.000
1.000
0.100
0.010
0.001
100000
SAMPLING RATE (SPS)
10000
1000000
IVDD
IVIO
IREF
Figure 28. Operating Currents vs. Sampling Rate


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