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AD7982 Datasheet(PDF) 7 Page - Analog Devices

Part No. AD7982
Description  18-Bit, 1 MSPS PulSAR 7 mW ADC in MSOP/LFCSP
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7982 Datasheet(HTML) 7 Page - Analog Devices

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AD7982
Data Sheet
Rev. D | Page 6 of 25
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, −40°C to +85°C, unless otherwise stated.1
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
THROUGHPUT RATE
800
kSPS
CONVERSION AND AQUISITION TIMES
Conversion Time: CNV Rising Edge to Data Available
tCONV
500
800
ns
Acquisition Time
tACQ
290
ns
Time Between Conversions
tCYC
1.25
μs
CNV PULSE WIDTH (CS MODE)
tCNVH
10
ns
SCK
SCK Period (CS Mode)
tSCK
22
ns
SCK Period (Chain Mode)
tSCK
23
ns
SCK Low Time
tSCKL
6
ns
SCK High Time
tSCKH
6
ns
SCK Falling Edge to Data Remains Valid
tHSDO
3
ns
SCK Falling Edge to Data Valid Delay
tDSDO
14
21
ns
CS MODE
CNV or SDI Low to SDO D17 MSB Valid
tEN
18
40
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance
tDIS
20
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge
tHSDICNV
10
ns
CHAIN MODE
SDI Valid Hold Time from CNV Rising Edge
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge
tSSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge
tHSDISCK
3
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
22
ns
1 See Figure 2 and Figure 3 for load conditions.
500µA
IOL
500µA
IOH
1.4V
TO SDO
CL
20pF
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
Y% VIO1
VIH2
VIL2
VIL2
VIH2
tDELAY
tDELAY
1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing


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