AD7264

Data Sheet

Rev. D | Page 6 of 29

TIMING SPECIFICATIONS

Table 2.

Parameter

Unit

Description

200

200

kHz min

34

MHz max

AD7264

20

20

MHz max

AD7264-5

ns max

560

560

ns max

AD7264

950

950

ns max

AD7264-5

13

13

ns min

Minimum time between end of serial read/bus relinquish

and next falling edge of CS

10

10

ns min

CS to SCLK setup time

15

15

ns max

three-state disabled

29

23

ns max

Data access time after SCLK falling edge

15

13

ns min

SCLK to data valid hold time

ns min

SCLK high pulse width

ns min

SCLK low pulse width

13

13

ns min

CS rising edge to falling edge pulse width

13

13

ns max

relinquish

5

5

ns min

35

35

ns max

2

2

μs min

Minimum CAL pin high time

2

2

μs min

Minimum time between the CAL pin high and the CS

falling edge

3

3

ns min

3

3

ns min

240

240

μs max

Internal reference, with a 1 μF decoupling capacitor

15

15

μs max

With an external reference, 10 μs typical

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the

Terminology section.

2 The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz.

CS

SCLK

15

19

THREE-STATE

23

4

20

THREE-

STATE

18

21

31

32

33

THREE-STATE

THREE-

STATE

Figure 2. Serial Interface Timing Diagram