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AD7264BCPZ Datasheet(PDF) 9 Page - Analog Devices

Part No. AD7264BCPZ
Description  1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7264BCPZ Datasheet(HTML) 9 Page - Analog Devices

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AD7264
Data Sheet
Rev. D | Page 8 of 29
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
AD7264
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
15 16 17 18 19 20 21 22 23 24
25
COUTD
26
COUTC
27
VDRIVE
28
DGND
29
COUTB
30
COUTA
31
DOUTB
32
DOUTA
33
AVCC
34
SCLK
35
CS
36
CAL
37
38
39
40
41
42
43
44
45
46
47
48
14
CA_CBVCC
AVCC
VA
VA+
AGND
AVCC
AGND
VB+
VB
AVCC
CC_CDVCC
AGND
Figure 3. 48-Lead LQFP Pin Configuration
COUTD
COUTC
VDRIVE
DGND
COUTB
COUTA
DOUTB
DOUTA
AVCC
SCLK
CAL
CS
CA_CBVCC
AVCC
VA
VA+
AGND
AVCC
AGND
VB+
VB
AVCC
CC_CDVCC
AGND
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR
NOISE AND MECHANICAL STRENGTH BENEFITS.
1
2
3
4
5
6
7
TOP VIEW
(Not to Scale)
AD7264
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
2, 7, 11, 20, 33, 41
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the
AD7264. All AVCC pins can be tied together. This supply should be decoupled to AGND with a 100 nF
ceramic capacitor per supply and a 10 μF tantalum capacitor.
1
CA_CBVCC
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and
Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
12
CC_CDVCC
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and
Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
4, 3
VA+, VA
Analog Inputs of ADC A. True differential input pair.
9, 10
VB+, VB
Analog Inputs of ADC B. True differential input pair.
43, 18
VREFA, VREFB
Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the
internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple
the reference. Provided the output is buffered, the on-chip reference can be taken from these pins
and applied externally to the rest of a system.
34
SCLK
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the
AD7264. This clock is also used as the clock source for the conversion process. A minimum of
33 clocks are required to perform the conversion and access the 14-bit result.
35
CS
Chip Select. Active low logic input. This input initiates conversions on the AD7264.
36
CAL
Logic Input. Initiates an internal offset calibration.
21
PD2
Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD1 and
PD0 pins. See Table 7.
22
PD1
Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD2 and
PD0 pins. See Table 7.
23
PD0/DIN
Logic Input/Data Input. Places the AD7264 in the selected shutdown mode in conjunction with the
PD2 and PD1 pins. See Table 7. If all gain selection pins, G0 to G3, are tied low, this pin acts as the
data input pin and all programming is via the control register (see Table 8). Data to be written to the
AD7264 control register is provided on this input and is clocked into the register on the falling edge
of SCLK.


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