NOIL1SM0300A

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9

Biasing

Table 9 summarizes the biasing signals required to drive

this image sensor. For optimization reasons of the biasing of

the column amplifiers with respect to power dissipation,

several biasing resistors are required. This optimization

results in an increase of signal swing and dynamic range.

Table 9. OVERVIEW OF BIAS SIGNALS

Signal[1]

Comment

Related Module

DC−Level

ADC_BIAS

ADC

693 mV

PRECHARGE_BIAS

Pixel array precharge

567 mV

BIAS_PGA

PGA

650 mV

BIAS_FAST

Column amplifiers

750 mV

BIAS_SLOW

Column amplifiers

450 mV

BIAS_COL

Column amplifiers

508 mV

1. Each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation.

Digital Signals

Depending on the operation mode (master or slave), the

pixel array of the image sensor requires different digital

control signals. The function of each of the signals is shown

in Table 10.

Table 10. OVERVIEW OF BIAS SIGNALS

Signal

I/O

Comments

LINE_VALID

Digital output

Indicates when valid data is at the outputs. Active high

FRAME_VALID

Digital output

Indicates when a valid frame is readout. Active high

INT_TIME_3

Digital I/O

In master mode: Output to indicate the triple slope integration time.

In slave mode: Input to control the triple slope integration time.

Active high

INT_TIME_2

Digital I/O

In master mode: Output to indicate the dual slope integration time.

In slave mode: Input to control the dual slope integration time.

Active high

INT_TIME_1

Digital I/O

In master mode: Output to indicate the integration time.

In slave mode: Input to control integration time.

Active high

RESET_N

Digital input

Sequencer reset. Active low

CLK

Digital input

Readout clock (80 MHz), sine or square clock

SPI_ENABLE

Digital input

Enable of the SPI

SPI_CLK

Digital input

Clock of the SPI. (Max. 20 MHz)

SPI_DATA

Digital I/O

Data line of the SPI. Bidirectional pin