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NOIL1SE0300A-QDC Datasheet(PDF) 5 Page - ON Semiconductor |
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NOIL1SE0300A-QDC Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 29 page NOIL1SM0300A www.onsemi.com 5 Frame Rate and Windowing Frame Rate The frame rate depends on the input clock, the Frame Overhead Time (FOT) and the Row Overhead Time (ROT). The frame period is calculated as follows Frame period = FOT + Nr. Lines * (ROT + Nr. Pixels * clock period) Example: read out of the full resolution at nominal speed (80 MHz pixel rate = 12.5 ns, GRAN<1:0>=10): Frame period = 7.8 ms + (480 * (400 ns + 12.5 ns * 640) = 4.039 ms => 247.6 fps. In case the sensor operates in subsampling, the ROT is enlarged with 8 clock periods. Table 3. FRAME RATE PARAMETERS Parameter Comment Clarification FOT Frame Overhead Time 1200 clock periods for GRAN<1:0> = 11 624 clock periods for GRAN<1:0> = 10 336 clock periods for GRAN<1:0> = 01 192 clock periods for GRAN<1:0> = 00 ROT Row Overhead Time 48 clock periods for GRAN<1:0> = 11 32 clock periods for GRAN<1:0> = 10 24 clock periods for GRAN<1:0> = 01 20 clock periods for GRAN<1:0> = 00 Nr. Lines Number of lines read out each frame Nr. Pixels Number of pixels read out each line clock period 1/80 MHz = 12.5 ns Windowing Windowing is achieved by the SPI interface. The starting point of the x- and y-address is uploadable, as well as the window size. The minimum step size in the x-direction is 8 pixels (only multiples of 8 can be chosen as start/stop addresses). The minimum step size in the y-direction is 1 line (every line can be addressed) in normal mode and 2 lines in subsampling mode. The window size in the x-direction is uploadable in register NB_OF_PIX. The window size in the y-direction is determined by the register FT_TIMER Table 4. FRAME RATE PARAMETERS Parameter Frame Rate (fps) Frame Readout (us) Comment 640 x 480 247.5 4038 640 x 240 488.3 2048 Subsampling 256 x 256 1076 929 Windowing Analog to Digital Converter The sensor has four 10-bit pipelined ADC on board. The ADCs are nominally operating at 20 Msamples/s. The input range of the ADC is between 0.75 and 1.75V. The analog input signal is sampled at 2.1 ns delay from the rising edge of the ADC clock. The digital output data appears at the output at 5.5 cycles later. This is at the 6th falling edge succeeding the sample moment. The data is delayed by 3.7 ns with respect to this falling edge. This is illustrated in Figure 6. Table 5. ADC PARAMETERS Parameter Specification Data rate 20 Msamples/s Input range 0.75 V − 1.75 V Quantization 10 bit DNL Typ. < 0.3 LSB INL Typ. < 0.7 LSB |
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