P55N02 datasheet(1/3 Pages) ETC

Part #	P55N02

Description	N-Channel Logic Level Enhancement, Mode Field Effect Transistor

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MAY-24-2001

N-Channel Logic Level Enhancement

Mode Field Effect Transistor

P55N02LD

TO-252 (DPAK)

NIKO-SEM

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

UNITS

Gate-Source Voltage

VGS

±20

V

TC = 25 °C

55

Continuous Drain Current

TC = 100 °C

ID

36

Pulsed Drain Current

1

IDM

140

Avalanche Current

IAR

20

A

Avalanche Energy

L = 0.1mH

EAS

140

Repetitive Avalanche Energy

2

L = 0.05mH

EAR

5.6

mJ

TC = 25 °C

60

Power Dissipation

TC = 100 °C

PD

38

W

Operating Junction & Storage Temperature Range

Tj, Tstg

-55 to 150

Lead Temperature (

1/

16” from case for 10 sec.)

TL

275

°C

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

TYPICAL

MAXIMUM

UNITS

Junction-to-Case

RθJC

2.5

Junction-to-Ambient

RθJA

65

Case-to-Heatsink

RθCS

0.7

°C / W

1Pulse width limited by maximum junction temperature.

2Duty cycle

≤ 1％

ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)

LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC

Drain-Source Breakdown Voltage

V(BR)DSS

VGS = 0V, ID = 250

µA

25

Gate Threshold Voltage

VGS(th)

VDS = VGS, ID = 250

µA

1

1.5

3

V

Gate-Body Leakage

IGSS

VDS = 0V, VGS = ±20V

±250

nA

VDS = 20V, VGS = 0V

25

Zero Gate Voltage Drain Current

IDSS

VDS = 20V, VGS = 0V, TJ = 125 °C

250

µA

1. GATE

2. DRAIN

3. SOURCE

PRODUCT SUMMARY

V(BR)DSS

RDS(ON)

ID

25

10m

Ω

55A

G

D

S

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