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K6F8016R6B Datasheet(PDF) 5 Page - Samsung semiconductor

Part # K6F8016R6B
Description  512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6F8016R6B Datasheet(HTML) 5 Page - Samsung semiconductor

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K6F8016R6B Family
Revision 1.0
October 2001
5
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
Input rising and falling time: 5ns
Input and output reference voltage: 0.9V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1. 1) CS1
≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or
2) 0
≤CS2≤0.2V(CS2 controlled)
2. Typical value are measured at TA=25
°C and not 100% tested.
Item
Symbol
Test Condition
Min
Typ2)
Max
Unit
Vcc for data retention
VDR
CS1
≥Vcc-0.2V1)
1.0
-
2.2
V
Data retention current
IDR
Vcc=1.2V, CS1
≥Vcc-0.2V1)
-
0.5
6
µA
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
CL1)
1. Including scope and jig capacitance
R22)
R12)
VTM3)
2. R1=3070
, R2=3150Ω
3. VTM =1.8V
AC CHARACTERISTICS(Vcc=1.65~2.2V, Industrial product: TA=-40 to 85
°C)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
Min
Max
Min
Max
Read
Read Cycle Time
tRC
70
-
85
-
ns
Address Access Time
tAA
-
70
-
85
ns
Chip Select to Output
tCO
-
70
-
85
ns
Output Enable to Valid Output
tOE
-
35
-
40
ns
UB, LB Access Time
tBA
-
70
-
85
ns
Chip Select to Low-Z Output
tLZ
10
-
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
25
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
25
0
25
ns
Output Disable to High-Z Output
tOHZ
0
25
0
25
ns
Output Hold from Address Change
tOH
10
-
10
-
ns
Write
Write Cycle Time
tWC
70
-
85
-
ns
Chip Select to End of Write
tCW
60
-
70
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
60
-
70
-
ns
UB, LB Valid to End of Write
tBW
60
-
70
-
ns
Write Pulse Width
tWP
50
-
60
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
20
0
25
ns
Data to Write Time Overlap
tDW
30
-
35
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns


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