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NTE21256 Datasheet(PDF) 2 Page - NTE Electronics

Part No. NTE21256
Description  262,144-Bit Dynamic Random Access Memory (DRAM)
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Manufacturer  NTE [NTE Electronics]
Direct Link  http://www.nteinc.com
Logo NTE - NTE Electronics

NTE21256 Datasheet(HTML) 2 Page - NTE Electronics

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Functional Description:
Device Initialization
Since the NTE21256 is a dynamic RAM with a single +5V supply, no power sequencing is required.
For power–up, an initial pause of 200
µs is necessary for the internal bias generator to establish the
proper substrate bias voltage. To initialize the nodes of the dynamic circuitry, a minimum of 8 active
cycles of the Row Address Strobe (RAS) has to be performed. This is also necessary after an ex-
tended inactive state of greater than 4ms.
Addressing (A0–A8)
For selecting one of the 262,144 memory cells, a total of 18 address bits are required. First 8 Row
Address bits are set up on pins A0 through A8 and latched into the row address latches by the Row
Address Strobe (RAS). Then the 9 column address bits are set up on pins A0 through A8 and latched
into the column address latches by the Column Address Strobe (CAS). All input addresses must be
stable on the falling edges of RAS and CAS. It should be noted that RAS is similar to a Chip Enable
in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select acti-
vating the column decoder and the input and output buffers.
Write Enable (WE)
The read or write mode is selected with the WE input. A logic high (VIH) on WE dictates read
mode; logic low (VIL) dictates write mode. The data input is disabled when read mode is selected.
When WE goes low prior to CAS, data output (DO) will remain in the high–impedance state for the
entire cycle permitting common I/O operation.
Data Input (DI)
Data is written during a write or read–modify–write cycle. The falling edge of CAS or WE strobes data
into the on–chip data latch. In an early write cycle, WE is brought low prior to CAS and the data is
strobed in by CAS with setup and hold times referenced to this signal.
Data Output (DO)
The output is three–state TTL compatible with a fan–out of two standard TTL loads. Data Out has
the same polarity as Data In. The output is in a high impedance state until CAS is brought low. In
a read cycle or read–write cycle, the output is valid after tRAC from transition of RAS when tRCD (Min)
is satisfied, or after tCAC from transition of CAS when the transition occurs after tRCD (Max). In an early
write cycle, the output is always in the high impedance state. In a delayed write or read–modify–write
cycle, the output will follow the sequence for the read cycle. With CAS going high the output returns
to the high impedance state within tOFF.
Hidden Refresh
RAS–only refresh cycle may take place while maintaining valid output data. This feature is referred
to as Hidden Refresh. Hidden Refresh is performed by holding CAS at VIL of a previous memory read
cycle.
Refresh Cycle
A refresh operation must be performed at least every 4ms to retain data. Since the output buffer is
in the high impedance state unless CAS is applied, the RAS–only refresh sequence avoids any signal
during refresh. Strobing each of the 256 row addresses (A0 through A7) with RAS, causes all bits
in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve
power.
Page Mode
Page–mode operation allows effectively faster memory access by maintaining the row address and
strobing random column addresses onto the chip. Thus, the time necessary to setup and strobe se-
quential row addresses for the same page is no longer required. The maximum number of columns
that can be addressed in sequence is determined by tRAS, the maximum RAS low pulse width.


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