IS42S16100C1 datasheet(29/79 Pages) ISSI

Part #	IS42S16100C1

Description	512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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IS42S16100C1

ISSI®

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

29

Rev. A

07/21/04

Interval Between Read and Write Commands

A read command can be interrupted and a new write

command executed while the read cycle is in progress,

i.e., before that cycle completes. Data corresponding to

the new write command can be input at the point new

write command is executed. To prevent collision

between input and output data at the DQn pins during

this operation, the

output data must be masked using the U/LDQM pins. The

interval (tCCD) between these commands must be at least

one clock cycle.

The selected bank must be set to the active state before

executing this command.

WRITE B0

READ A0

COMMAND

U/LDQM

DQ

CLK

DIN B0

DIN B2

DIN B1

DIN B3

tCCD

HI-Z

READ (CA=A, BANK 0)

WRITE (CA=B, BANK 0)

CAS latency = 2, 3, burstlength = 4

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IS42S16100C1 Datasheet(PDF) 29 Page - Integrated Silicon Solution, Inc

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