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ADS8412 Datasheet(PDF) 5 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part No. ADS8412
Description  16-BIT, 2 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
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Maker  BURR-BROWN [Burr-Brown (TI)]
Homepage  http://www.burr-brown.com
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ADS8412 Datasheet(HTML) 5 Page - Burr-Brown (TI)

 
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TIMING CHARACTERISTICS
ADS8412
SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
All specifications typical at –40
°C to 85°C, +VA = +VBD = 5 V(1)(2)(3)
PARAMETER
MIN
TYP
MAX
UNIT
tCONV
Conversion time
340
400
ns
tACQ
Acquisition time
100
ns
tpd1
CONVST low to BUSY high
30
ns
tpd2
Propagation delay time, end of conversion to BUSY low
5
ns
tw1
Pulse duration, CONVST low
20
ns
tsu1
Setup time, CS low to CONVST low
0
ns
tw2
Pulse duration, CONVST high
20
ns
CONVST falling edge jitter
10
ps
tw3
Pulse duration, BUSY signal low
Min(tACQ)
ns
tw4
Pulse duration, BUSY signal high
370
ns
Hold time, first data bus data transition (RD low, or CS low for read
th1
40
ns
cycle, or BYTE input changes) after CONVST low
td1
Delay time, CS low to RD low (or BUSY low to RD low)
0
ns
tsu2
Setup time, RD high to CS high
0
ns
tw5
Pulse duration, RD low
50
ns
ten
Enable time, RD low (or CS low for read cycle) to data valid
20
ns
td2
Delay time, data hold from RD high
0
ns
td3
Delay time, BYTE rising edge or falling edge to data valid
2
20
ns
tw6
Pulse duration, RD high
20
ns
tw7
Pulse duration, CS high
20
ns
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
th2
50
ns
falling edge
tsu3
Setup time, BYTE transition to RD falling edge
0
ns
th3
Hold time, BYTE transition to RD falling edge
0
ns
tdis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
20
ns
td5
Delay time, end of conversion to MSB data valid
10
ns
Byte transition setup time, from BYTE transition to the next BYTE
tsu4
50
ns
transition
td6
Delay time, CS rising edge to BUSY falling edge
50
ns
td7
Delay time, BUSY falling edge to CS rising edge
50
ns
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
tsu(AB)
60
340
ns
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
tsu5
MAX(tCONV) + MAX(td5)
ns
current conversion
Hold time, data (MSB) from previous conversion hold valid from falling
th4
MIN(tCONV)
ns
edge of CONVST
(1)
All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2)
See timing diagrams.
(3)
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
5


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