9 / 12 page
CY25823
Document #: 38-07579 Rev. *C
Page 9 of 12
Application Schematic[2,3]
Notes:
1. Not 100% tested, guaranteed by design.
2. VDD and VDDA should be tied together and connected to 3.3V.
3. VSSIREF and VSS are tied together and are common ground.
TR / TF
CLKOUT and CLKOUT# Rise and Fall Times Measured from VOL = 0.175 to
VOH = 0.525V
175
700
ps
TRFM
Rise/Fall Matching
Determined as a fraction of
2*(TR –TF)/(TR + TF)
–20
%
Tstable[1]
All clock stabilization from Power-up
–
3.0
ms
∆TR
Rise Time Variation
–
125
ps
∆TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
660
850
mv
VLOW
Voltage Low
–150
–
mv
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mv
VOVS
Maximum Overshoot Voltage
–
VHIGH +
0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
Measure SE
–
0.2
V
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
V DDA
VDD
VDD
0.1
µF
CLKOUT
CLKOUT#
16
9
12
11
33Ω
33Ω
IREF
475Ω
VSSIREF
VSS
VSSA
Separate Ground
14
13
10
15
10ΚΩ
VDD
REFOUT/SEL
33Ω
PW RDW N
5
6
SCLOCK
SDA TA
CLKIN
S2
S3
S1
7
8
4
3
1
2
R1
R2
R3
R4
R5
C1
49.9Ω
49.9Ω
1%
R7
R6
1%
1%
5%
5%
5%
5%
Source
Termination
Figure 4. Application Schematic
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
