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SN74LVTH126 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN74LVTH126
Description  3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74LVTH126 Datasheet(HTML) 1 Page - Texas Instruments

 
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SN54LVTH126, SN74LVTH126
3.3V ABT QUADRUPLE BUS BUFFERS
WITH 3STATE OUTPUTS
SCBS746B − JULY 2000 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
These bus buffers are designed specifically for
low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
The ’LVTH126 devices feature independent line
drivers with 3-state outputs. Each output is in the
high-impedance state when the associated
output-enable (OE) input is low.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube
SN74LVTH126D
LVTH126
SOIC − D
Tape and reel
SN74LVTH126DR
LVTH126
SOP − NS
Tape and reel
SN74LVTH126NSR
LVTH126
−40
°C to 85°C
SSOP − DB
Tape and reel
SN74LVTH126DBR
LXH126
−40 C to 85 C
TSSOP − PW
Tube
SN74LVTH126PW
LXH126
TSSOP − PW
Tape and reel
SN74LVTH126PWR
LXH126
TVSOP − DGV
Tape and reel
SN74LVTH126DGVR
LXH126
CDIP − J
Tube
SNJ54LVTH126J
SNJ54LVTH126J
−55
°C to 125°C
CFP − W
Tube
SNJ54LVTH126W
SNJ54LVTH126W
−55 C to 125 C
LCCC − FK
Tube
SNJ54LVTH126FK
SNJ54LVTH126FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVTH126 ...J OR W PACKAGE
SN74LVTH126 ...D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
32
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
NC − No internal connection
SN54LVTH126 . . . FK PACKAGE
(TOP VIEW)


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