ONET2501PA

155Mbps TO 2.5Gbps LIMITING AMPLIFIER

SLLS602A − MARCH 2004 − REVISED JULY 2004

3

POST OFFICE BOX 655303

bandgap voltage and bias generation

The ONET2501PA limiting amplifier is supplied by a single 3.3-V

±10% supply voltage connected to the VCC

and VCCO pins. This voltage is referred to ground (GND).

An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other

internally required voltages and bias currents are derived.

package

For the ONET2501PA a small footprint 3 mm

× 3 mm 16-pin QFN Package is used, with a lead pitch of 0,5 mm.

The pinout is shown in Figure 2.

VCC

DIN+

DIN−

VCC

VCCO

DOUT+

DOUT−

OUTPOL

Figure 2. Pinout of ONET2501PA in a 3 mm

y 3 mm 16-Pin QFN Package

terminal functions

The following table shows a pin description for the ONET2501PA in a 3 mm x 3 mm 16-pin QFN package.

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

VCC

1, 4

Supply

3.3-V

±10% supply voltage

DIN

+

2

Analog in

Noninverted data input. On-chip 50-

Ω terminated to VCC.

DIN–

3

Analog in

Inverted data input. On-chip 50-

Ω terminated to VCC.

TH

5

Analog in

LOS threshold adjustment with resistor to GND.

DISABLE

6

CMOS in

Disables CML output stage when set to high level.

LOS

7

CMOS out

High level indicates that the input signal amplitude is below the programmed threshold level.

GND

8, 16, EP

Supply

Circuit ground. Exposed die pad (EP) must be grounded.

OUTPOL

9

CMOS in

Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects

normal polarity. Low level selects inverted polarity.

DOUT–

10

CML out

Inverted data output. On-chip 50-

Ω back-terminated to VCCO

DOUT+

11

CML out

Noninverted data output. On-chip 50-

Ω back-terminated to VCCO

VCCO

12

Supply

3.3-V

±10% supply voltage for output stage

RSSI

13

Analog out

Analog output voltage proportional to the input data amplitude. Indicates the strength of the received

signal (RSSI).

COC1

14

Analog

Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin

and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

COC2

15

Analog

Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin

and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).