ADM1060ARU datasheet(17/45 Pages) AD

Part #	ADM1060ARU

Description	Communications System Supervisory/Sequencing Circuit

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PROGRAMMING ADM1060

ADM1060

– 17 –

REV. PrJ 11/02

PRELIMINARY TECHNICAL DATA

PROGRAMMABLE LOGIC BLOCK ARRAY

The ADM1060 contains a Programmable Logic Block

Array (PLBA). This block is the logical core of the

device. The PLBA (and the PDBs- see next section) is

what provides the sequencing function of the ADM1060.

The assertion of the 9 Programmable Driver Outputs

(PDO) is controlled by the PLBA. The PLBA comprises

of 9 macrocells, 1 per PDO Channel. The main

components of the macrocells are 2 Wide AND- OR

gates, as shown in Figure 4. Each AND gate represents a

function (A and B) which can be used independently to

control the assertion of the PDO pin. There are 21 inputs

to each of these AND gates. These are:-

• The logic outputs of all 7 of the Supply Fault Detectors

• The 4 GPI logic inputs

• The Watchdog fault detector (Latched and Pulsed)

• The delayed output of any of the other macrocells (the

output of a macrocell cannot be an input to itself, since

this would result in a non- terminating loop).

All 21 inputs are hardwired to both function A and

function B AND gates. The user can then select which of

these inputs controls the output. This is done using 2

control signals, IMK (a masking bit, setting it ignores the

relevant input) and POL (a polarity bit, setting it inverts

the input before it is applied to the AND gate). The effect

of setting these bits can be seen in figure 4 below. The

inverting gate shown is an X-OR gate, resulting in the

following truth table:-

POL

INPUT SIGNAL

X-OR OUTPUT

00

0

01

1

10

1

11

0

Table 25. Truth Table for PLB Input Inversion

The last 2 entries in the truth table show, that with the

INVERT bit set, the X-OR output is always the inverse of

the input.

Similarly, the ignore gate shown is an OR gate, resulting

in the following truth table:-

IMK

INPUT SIGNAL

OR OUTPUT

00

0

01

1

10

1

11

1

Table 26 Truth Table for PLB Input Masking

It can be seen here that once the IMK bit is set the OR

output is always 1, regardless of the input, thus ignoring

it. Overleaf is a detailed diagram of the 21 inputs and the

registers required to program them. Those shown are just

for function A of PLB1 but function B and all of the

functions in the other 8 PLB’s are programmed exactly the

same way. An Enable register allows the user to use

function A or B or both. The output of functions A and/

or B is inputted to a Programmable Delay Block (PDB)

where a delay can be programmed on both the rising and

falling edge of an input (see next section). The output of

this PDB block can be progammed to invert before one or

any of the PDO pins is asserted.

The control bits for these macrocells are stored locally in

latches which are loaded at power up. These latches can

also be updated via the serial interface. The registers

containing the macrocell control bits, and the function of

each bit are defined in the tables overleaf.

Figure 4. Simplified Programmable Logic Block Macrocell Schematic

SIGNAL INPUTS

IMK ( IGNORE)

POL (INVERT)

ENABLE

FUNCTION A

ENABLE

FUNCTION B

PROGRAMMABLE

DELAY

BLOCK

PLBOUT

INVERT

OUTPUT

2 wide AND gates

(20 inputs)

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