EVAL-AD7625FMCZ datasheet(6/25 Pages) AD

Part #	EVAL-AD7625FMCZ

Description	16-Bit, 6 MSPS, PulSAR Differential ADC

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Manufacturer	AD [Analog Devices]

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Data Sheet

AD7625

Rev. B | Page 5 of 24

TIMING SPECIFICATIONS

VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Time Between Conversions1

tCYC

166

10,000

ns

Acquisition Time

tACQ

40

ns

CNV± High Time

tCNVH

10

40

ns

CNV± to D± (MSB) Delay

tMSB

145

ns

CNV± to Last CLK± (LSB) Delay

tCLKL

110

ns

CLK± Period2

tCLK

(tCYC − tMSB + tCLKL)/n

4

3.33

ns

CLK± Frequency

fCLK

250

300

MHz

CLK± to DCO± Delay (Echoed-Clock Mode)

tDCO

0

4

7

ns

DCO± to D± Delay (Echoed-Clock Mode)

tD

0

1

ns

CLK± to D± Delay

tCLKD

0

4

7

ns

1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid.

2 For the minimum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) that are read. In echoed-clock interface

mode, n = 16; in self-clocked interface mode, n = 18.

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