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NTE2053 Datasheet(PDF) 2 Page - NTE Electronics

Part No. NTE2053
Description  Integrated Circuit 8-Bit MPU Compatible A/D Converter
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Maker  NTE [NTE Electronics]
Homepage  http://www.nteinc.com
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NTE2053 Datasheet(HTML) 2 Page - NTE Electronics

   
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Electrical Characteristics: (VCC = 5V, TA = 0° to +70°C, fCLK = 640kHz unless otherwise specified)
Parameter
Test Conditions
Min
Typ
Max
Unit
Total Unadjusted Error (Note 4)
VREF/2 = 2.500V
±1/2
LSB
VREF/2 Input Resistance
2.5
8.0
k
Analog Input Voltage Range
V(+) or V(–), Note 5
GND–0.05
VCC+0.05
V
DC Common–Mode Error
Over Analog Input Voltage Range
±1/16
±1/8
LSB
Power Supply Sensitivity
VCC = 5V ±10% Over Allowed
VIN(+) and VIN(–) Voltage Range,
Note 5
±1/16
±1/8
LSB
Note 4. The NTE2053 A/D does not require a zero adjust.
Note 5. For VIN(–) ≥ VIN(+) the digital output code will be 0000 0000. Two on–chip diodes are tied
to each analog input which will forward conduct for analog input voltages one diode drop bel-
wo GND or one diode drop greater than the VCC supply. Be careful, during testing at low VCC
levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct – espe-
cially at elevated temperatures, and cause errors for analog inputs near full–scale. The spec
allows 50mV forward bias of either diode. This means that as long as the analog VIN does
not exceed the supply voltage by more than 50mV, the output code will be correct. To
achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply
voltage of 4.950V over temperature variations, initial tolerance, and loading.
AC Electrical Characteristics: (VCC = 5V, TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Conversion Time
TC
fCLK = 640kHz, Note 7
103
114
µs
Note 6, Note 7
66
73
1/fCLK
Clock Frequency
fCLK
VCC = 5V, Note 6
100
640
1460
kHz
Clock Duty Cycle
Note 6
40
60
%
Conversion Rate in Free–Running
Mode
CR
INTR tied to WR with
CS = 0V, fCLK = 640kHz
8770
conv/s
Width of WR Input (Start Pulse Width)
tW(WR)L
CS = 0, Note 8
100
ns
Access Time (Delay from Falling Edge
of RD to Output Data Valid)
tACC
CL = 100pF
135
200
ns
TRI–STATE Control (Delay from Rising
Edge of RD to Hi–Z State)
t1H, t0H
CL = 10pF, RL = 10k
125
200
ns
Delay from Falling Edge of WR or RD
to Reset of INTR
tWI, tRI
300
450
ns
Input Capacitance of Logic
Control Inputs
CIN
5
7.5
pF
TRI–STATE Output Capacitance
(Data Buffers)
COUT
5
7.5
pF
Note 6. Accuracy is guaranteed at fCLK = 640kHz. At higher clock frequencies accuracy can de-
grade. For lower clock frequencies, the duty cycle limits can be extended so long as the mini-
mum clock high time interval or minimum clock low time interval is no less than 275ns.
Note 7. With an asynchronous start pulse, up to 8 clock periods may be required before the internal
clock phases are proper to start the conversion process. The start request is internally
latched.
Note 8. The CS input is assumed to bracket the WR strobe input and therefore timing is dependent
on the WR pulse width. An arbitrary wide pulse width will hold the converter on a reset mode
and the start of conversion is initiated by the low to high transition of the WR pulse.


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