AD7356BRUZ datasheet(13/21 Pages) AD

Part #	AD7356BRUZ

Description	Differential Input, Dual, Simultaneous Sampling

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Manufacturer	AD [Analog Devices]

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AD7356

Data Sheet

Rev. B | Page 12 of 20

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7356 is a high speed, dual, 12-bit, single-supply, successive

approximation analog-to-digital converter (ADC). The device

operates from a 2.5 V power supply and features throughput

rates of up to 5 MSPS.

The AD7356 contains two on-chip differential track-and-hold

amplifiers, two successive approximation ADCs, and a serial

interface with two separate data output pins. The part is housed

in a 16-lead TSSOP, offering the user considerable space-saving

advantages over alternative solutions.

The serial clock input accesses data from the part but also provides

the clock source for each successive approximation ADC. The

AD7356 has an on-chip 2.048 V reference. If an external reference

is desired the internal reference can be overdriven with a reference

value ranging from (2.048 V + 100 mV) to VDD. If the internal

reference is to be used elsewhere in the system, then the

reference output needs to be buffered first. The differential

analog input range for the AD7356 is VCM ± VREF/2.

The AD7356 features power-down options to allow power

saving between conversions. The power-down feature is

implemented via the standard serial interface, as described

in the Modes of Operation section.

CONVERTER OPERATION

The AD7356 has two successive approximation ADCs, each

based around two capacitive DACs. Figure 14 and Figure 15

show simplified schematics of one of these ADCs in acquisition

and conversion phase. The ADC comprises a control logic, a

SAR, and two capacitive DACs. In Figure 14 (the acquisition

phase), SW3 is closed, SW1 and SW2 are in Position A, the

comparator is held in a balanced condition, and the sampling

capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

A

B

SW2

CS

VIN+

VIN–

VREF

Figure 14. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 15), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and charge redistribution

DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. The output impedances of

the sources driving the VIN+ and VIN− pins must be matched;

otherwise, the two inputs may have different settling times,

resulting in errors.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

A

B

SW2

CS

VIN+

VIN–

VREF

Figure 15. ADC Conversion Phase

ANALOG INPUT STRUCTURE

Figure 16 shows the equivalent circuit of the analog input structure

of the AD7356. The four diodes provide ESD protection for the

analog inputs. Care must be taken to ensure that the analog input

signals never exceed the supply rails by more than 300 mV.

This causes these diodes to become forward biased and start

conducting into the substrate. These diodes can conduct up

to 10 mA without causing irreversible damage to the part.

The C1 capacitors in Figure 16 are typically 8 pF and can

primarily be attributed to pin capacitance. The R1 resistors

are lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 30 Ω.

The C2 capacitors are the sampling capacitors of the ADC

with a capacitance of 32 pF typically.

VDD

C1

D

VIN+

R1 C2

VDD

C1

D

VIN–

R1 C2

Figure 16. Equivalent Analog Input Circuit,

Conversion Phase–Switches Open,

Track Phase—Switches Closed

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