AD7191 datasheet(4/21 Pages) AD

Part #	AD7191

Description	Sigma-Delta ADC for Bridge Sensors

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AD7191

Rev. A | Page 3 of 20

SPECIFICATIONS

AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V; REFIN(+) = AVDD; REFIN(−) = AGND; MCLK = 4.92 MHz; all

specifications TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1

AD7191B

Unit

Test Conditions/Comments

Output Data Rate

10, 50, 60, 120

Hz nom

No Missing Codes2

24

Bits min

Resolution

See the RMS Noise and Resolution Specifications

section

RMS Noise and Update Rates

See the RMS Noise and Resolution Specifications

section

Integral Nonlinearity

Gain = 12

±10

ppm of FSR max

±2 ppm typical, AVDD = 5 V

±15

ppm of FSR max

±2 ppm typical., AVDD = 3 V

Gain > 1

±5

ppm of FSR typ

AVDD = 5 V

±12

ppm of FSR typ

AVDD = 3 V

Offset Error

±150/gain

μV typ

Offset Error Drift vs. Temperature

±150/gain

nV/°C typ

Gain = 1 or 8

±5

nV/°C typ

Gain = 64 or 128

Offset Error Drift vs. Time

25

nV/1000 hours typ

Gain = 64 or 128

Gain Error

±0.4

% typ

Gain Drift vs. Temperature

±1

ppm/°C typ

Gain Drift vs. Time

10

ppm/1000 hours typ

Gain = 1

Power Supply Rejection

90

dB typ

Gain = 1, AIN = 1 V

95

dB min

110 dB typical, gain > 1, AIN = 1 V/gain

Normal Mode Rejection2

Internal Clock

@ 50 Hz, 60 Hz

100

dB min

10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz

74

dB min

50 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz

@ 60 Hz

97

dB min

60 Hz output data rate, 60 ± 1 Hz.

External Clock

@ 50 Hz, 60 Hz

120

dB min

10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

82

dB min

50 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.

@ 60 Hz

120

dB min

60 Hz output data rate, 60 ± 1 Hz

Common-Mode Rejection

@ DC2

100

dB min

Gain = 1, AIN = 1 V

@ DC

110

dB min

Gain > 1, AIN = 1 V/gain

@ 50 Hz, 60 Hz2

120

dB min

10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz

@ 50 Hz, 60 Hz2

120

dB min

50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz

(60 Hz output data rate)

ANALOG INPUTS

Differential Input Voltage Ranges

±VREF/gain

V nom

VREF = REFIN(+)

− REFIN(−), gain = 1, 8, 64, or 128

±(AVDD – 1.25 V)/gain

V min/V max

Gain > 1

Absolute AIN Voltage Limits2

AGND + 250 mV

V min

AVDD

− 250 mV

V max

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