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AD7171 Datasheet(PDF) 4 Page - Analog Devices

Part No. AD7171
Description  16-Bit, Low Power, Sigma-Delta ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7171 Datasheet(HTML) 4 Page - Analog Devices

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Data Sheet
AD7171
Rev. C | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VREF = VDD, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
AD7171B1
Unit
Test Conditions/Comments
Min
Typ
Max
ADC CHANNEL
Output Data Rate (fADC)
125
Hz
Settling time = 3/fADC
No Missing Codes2
16
Bits
Resolution Peak-to-Peak (p-p)
16
Bits
VINx = 0 V, VREF = VDD
Effective Resolution (ENOB)
16
Bits
VINx = 0 V, VREF = VDD
RMS Noise
See Table 7
µV
VINx = 0 V, VREF = VDD
Integral Nonlinearity
±0.4
LSB
Offset Error
±200
μV
Offset Error Drift vs. Temperature
±250
nV/°C
Full-Scale Error
±0.015
% of FS
Gain Drift vs. Temperature
±0.07
LSB/°C
Power Supply Rejection
85
dB
VINx = 1 V
ANALOG INPUTS
Differential Input Voltage Range
±VREF
V
VREF = REFIN(+) − REFIN(−)
Absolute AINx Voltage Limits2
GND − 0.03
VDD + 0.03
V
Average Input Current2
±400
nA/V
Input current varies with input voltage
Average Input Current Drift
±60
pA/V/°C
DC Common-Mode Rejection
90
dB
VINx = 1 V
REFERENCE
External REFIN Voltage
VDD
V
REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range2
0.5
VDD
V
Absolute REFIN Voltage Limits2
GND − 0.03
VDD + 0.03
V
Average Reference Input Current
400
nA/V
Average Reference Input Current Drift
±0.15
nA/V/°C
DC Common-Mode Rejection
110
dB
INTERNAL CLOCK
Frequency2
64 − 5%
64 + 5%
kHz
LOGIC INPUTS
SCLK, PDRST2
Input Low Voltage, VINL
0.4
V
VDD = 3 V
0.8
V
VDD = 5 V
Input High Voltage, VINH
1.8
V
VDD = 3 V
2.4
V
VDD = 5 V
SCLK (Schmitt-Triggered Input)2
Hysteresis
100
mV
VDD = 3 V
140
mV
VDD = 5 V
Input Currents
±2
µA
VIN = VDD or GND
Input Capacitance
5
pF
All digital inputs


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