LC75886PW

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11

(2) When CL is stopped at the high level

Note: B0 to B3, A0 to A3 ······ CCB address

DD ························· Direction data

 CCB address ········“42H”

 D1 to D171 ··········Display data

 OC ····················RC oscillator operating mode/external clock operationg mode switching control data

 PC50, PC51 ·········General-purpose output port/clock output port/segment output port switching control data

 KSC ··················Key scan operation enabled/disabled state setting control data

 S0, S1 ················Sleep control data

 K0, K1 ···············Key scan output/segment output switching control data

 P0 to P2 ··············Segment output port/general-purpose output port switching control data

 SC ····················Segment on/off control data

 FC0 to FC2 ··········Common and segment output waveform frame frequency control data

B1

B0

D2

D1

1

0

D50

KSC

DD

(3 bits)

Control data (12 bits)

Display data (57 bits)

DI

CL

CE

0

0

0

D53

1

0

0

B3

B2

A1

A0

A3

A2

D51

D55

D54

D56

SC

P2

P1

P0

0

0

1

K1

S0 S1 K0

D52

D47 D48 D49

PC51

PC50

OC

D57

DO

B1

B0

D59

D58

1

0

0

0

0

1

0

0

B3

B2

A1

A0

A3

A2

FC2

FC1

FC0

0

1

0

1

0

0

0

0

0

0

0

0

D114

D113

D112

D111

D110

D109

D108

D107

D106

D105

D104

B1

B0

1

0

0

0

0

1

0

0

B3

B2

A1

A0

A3

A2

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

D171

D170

D169

D168

D167

D166

D165

D164

D163

D162

D161

D116

D115

DD

(3 bits)

Control data (12 bits)

Display data (57 bits)

DD

(3 bits)

Fixed data (12 bits)

Display data (57 bits)