LC75879PT

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3

Parameter

Symbol

Pin

Conditions

Ratings

Unit

min

typ

max

Hysteresis

VH

CE, CL, DI, INH

0.03VDD

V

Input high level

current

IIH1

CE, CL, DI, INH

VI = 6.3 V

5.0

A

IIH2

OSCI

VI = VDD: External

clock operating mode

5.0

Input low level

current

IIL1

CE, CL, DI, INH

VI = 0 V

5.0

A

IIL2

OSCI

VI = 0 V: External

clock operating mode

5.0

Output high level

voltage *1

VOH1

S1 to S69

IO = 20 A

VDD00.9

V

VOH2

COM1 to COM4

IO = 100 A

VDD00.9

VOH3

P1 to P8

IO = 1mA

VDD0.9

Output low level

voltage

VOL1

S1 to S69

IO = 20 A

0.9

V

VOL2

COM1 to COM4

IO = 100 A

0.9

VOL3

P1 to P8

IO = 1 mA

0.9

Output middle

level

voltage

*1

*2

VMID1

S1 to S69

1/3 bias IO = 20 A

2/3VDD0

0.9

2/3VDD0

+0.9

V

VMID2

S1 to S69

1/3 bias IO = 20 A

1/3VDD0

0.9

1/3VDD0

+0.9

VMID3

COM1 to COM4

1/3 bias IO = 100 A

2/3VDD0

0.9

2/3VDD0

+0.9

VMID4

COM1 to COM4

1/3 bias IO = 100 A

1/3VDD0

0.9

1/3VDD0

+0.9

Oscillator

frequency

fosc

Internal

oscillator circuit

Internal oscillator

operating mode

240

300

360

kHz

Current drain

IDD1

VDD

Power-saving mode

100

A

IDD2

VDD

VDD = 6.3 V

Output open

Internal oscillator

operating mode

1000

2000

IDD3

VDD

VDD = 6.3 V

Output open

External clock

operating mode

fCK = 300 kHz

VIH2 = 0.5VDD

VIL2 = 0.1VDD

1000

2000

Note: *1. VDD0 = 0.70VDD to VDD

Note: *2. Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.)

To the common and segment drivers

[Figure 1]

VDD2

VDD1

Except these resistors.

CONTRAST

ADJUSTER

VDD

VSS

VDD0

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.