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LC75812PT Datasheet(PDF) 9 Page - ON Semiconductor |
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LC75812PT Datasheet(HTML) 9 Page - ON Semiconductor |
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9 / 55 page  LC75812PT www.onsemi.com 9 Pin Functions Pin Pin No. Function Active I/O Handling when unused S1 to S64 S65/COM9 1 to 64 65 Segment driver outputs. S65/COM9 can be used as common driver output pin under the "set display technique" instruction. - O OPEN COM1 to COM8 73 to 66 Common driver outputs. - O OPEN KS1/P1 KS2/P2 KS3 to KS6 KS7/P3 74 75 76 to 79 85 Key scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. KS1/P1, KS2/P2, and KS7/P3 can be used as general-purpose output ports under the "set key scan output port/general-purpose output port state" instruction. - O OPEN KI1 to KI5 80 to 84 Key scan inputs. These pins have built-in pull-down resistors. H I GND OSC 95 Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. This pin can also be used as the external clock input pin with the "set display technique" instruction. - I/O VDD CE 98 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data H I GND CL 99 I DI 100 - I DO 97 - O OPEN INH 96 Input that turns the display off, disables key scanning, and forces the general-purpose output ports low. When INH is low (VSS): Display off S1 to S64=”L” (VLCD4) S65/COM9=”L” (VLCD4) COM1 to COM8=”L” (VLCD4) General-purpose output ports P1 to P3=low (VSS) Key scanning disabled: KS1 to KS7=low (VSS) All the key data is reset to low. When INH is high (VDD): Display on The state of the pins as key scan output pins or general-purpose output ports can be set with the "set key scan output port/general-purpose output port state" instruction. Key scanning is enabled. However, serial data can be transferred when the INH pin is low. L I VDD TEST 94 This pin must be connected to ground. - I - VLCD0 88 LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V. Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. - O OPEN VLCD1 89 LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 (VLCD - VLCD4) voltage level externally. - I OPEN VLCD2 90 LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally. - I OPEN Continued on next page. |
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