Powerline Modules

500Mbps Module

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[3]

Module Interface

Module connectivity is provided via a 50 way 1.27mm pitch gold pin header.

Pin Number

Pin Name

MII

RGMII

Type

Description

1

VDD

PWR

+3.3V

2

VSS

PWR

Ground

3

VDD

PWR

+3.3V

4

VSS

PWR

Ground

5

VNET_IO

PWR

+2.5V / +3.3V

6

TXRX+

I/O

Differential TXRX signal, connects to coupling transformer

7

TXRX-

I/O

Differential TXRX signal, connects to coupling transformer

8

VSS

PWR

Ground

9

-

Reserved pin

10

-

Reserved pin

11

RESET#

I

Resets all IC logic when low

12

GPIO0

I/O

Strap: ENET_SEL[0]

13

GPIO1

I/O

Strap: ENET_SEL[1]; Push-button: Simple connect

14

GPIO2

I/O

Strap: ANEN; Push-button: Factory default

15

-

Reserved pin

16

GPIO4

I/O

Strap: SPEED_SEL[0]

17

GPIO5

I/O

Strap: MD_A3

18

GPIO6

I/O

Strap: CFG_SEL

19

GPIO7

I/O

Strap: MD_A4

20

GPIO8

I/O

Strap: MP_SEL; LED: Powerline Tx/Rx Link

21

GPIO3

I/O

Strap: ISODEF; LED: Ethernet Tx/Rx Link

22

GPIO10

I/O

Strap: BM_SEL

23

GPIO11

I/O

Strap: SPEED_SEL[1]; LED: Power

24

ZC_IN

I/O

Zero-cross detection signal

25

MDIO

I/O

Management Data Interface Data Line

26

MDC

Management Data Interface Clock Line

27

-

Reserved pin

28

-

Reserved pin

29

VSS

PWR

Ground

30

MRX_D0

RD0

MII / RGMII: Receive Data Bits (MAC)

31

MRX_D1

RD1

MII / RGMII: Receive Data Bits (MAC)

32

MRX_D2

RD2

MII / RGMII: Receive Data Bits (MAC)

33

MRX_D3

RD3

MII / RGMII: Receive Data Bits (MAC)

34

COL

MII: Collision Detected

35

MRX_CLK

RXC

MII / RGMII: Receive Clock (MAC)