AD9863BCPZRL-50 datasheet(4/41 Pages) AD

Part #	AD9863BCPZRL-50

Description	Transceiver for Broadband Applications

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Data Sheet

AD9863

Rev. B | Page 3 of 40

Tx PATH SPECIFICATIONS

FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω

1; TxPGA = 20 dB; AVDD = DVDD = 3.3 V,

unless otherwise noted.

Table 1.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

Tx PATH GENERAL

Resolution

Full

IV

12

Bits

Maximum DAC Update Rate

Full

IV

200

MHz

Maximum Full-Scale Output Current

Full

IV

20

mA

Full-Scale Error

Full

V

1%

Gain Mismatch Error

25°C

IV

−3.5

+3.5

% FS

Offset Mismatch Error

Full

IV

−0.1

+0.1

% FS

Reference Voltage

Full

V

1.23

V

Output Capacitance

Full

V

5

pF

Phase Noise (1 kHz Offset, 6 MHz Tone)

25°C

V

−115

dBc/Hz

Output Voltage Compliance Range

Full

IV

−1.0

+1.0

V

TxPGA Gain Range

Full

V

20

dB

TxPGA Step Size

Full

V

0.10

dB

Tx PATH DYNAMIC PERFORMANCE

(IOUTFS = 20 mA; FOUT = 1 MHz)

SNR

Full

IV

70.8

71.6

dB

SINAD

Full

IV

64.3

71

dB

THD

Full

IV

−79

−66.3

dBc

SFDR, Wide Band (DC to Nyquist)

Full

IV

68.5

77

dBc

SFDR, Narrow Band (1 MHz Window)

Full

IV

72.8

81

dBc

1 See Figure 2 for description of the TxDAC termination scheme.

TxDAC

50



50



Figure 2. Diagram Showing Termination of 100 Ω Differential

Load for Some TxDAC Measurements

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