AD9861BCPZ-80 datasheet(7/52 Pages) AD

Part #	AD9861BCPZ-80

Description	Transceiver for Broadband Applications

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AD9861

Data Sheet

Rev. A | Page 6 of 51

TIMING SPECIFICATIONS

Table 5. AD9861-50 and AD9861-80

Parameter

Temp

Test Level

Min

Typ

Max

Unit

INPUT CLOCK

CLKIN Clock Rate (PLL Bypassed)

Full

IV

1

200

MHz

PLL Input Frequency

Full

IV

16

200

MHz

PLL Ouput Frequency

Full

IV

32

350

MHz

TxPATH DATA

Setup Time (HD20 Mode, Time Required Before Data Latching

Edge)

Full

V

5

ns (see Clock

Distribution Block

section)

Hold Time (HD20 Mode, Time Required After Data Latching Edge)

Full

V

–1.5

ns (see Clock

Distribution Block

section)

Latency 1× Interpolation (data in until peak output response)

Full

V

7

DAC Clock Cycles

Latency 2× Interpolation (data in until peak output response)

Full

V

35

DAC Clock Cycles

Latency 4× Interpolation (data in until peak output response)

Full

V

83

DAC Clock Cycles

RxPATH DATA

Output Delay (HD20 Mode, tOD)

Full

V

–1.5

ns (see Clock

Distribution Block

section)

Latency

Full

V

5

ADC Clock Cycles

Table 6. Explanation of Test Levels

Level

Description

I

100% production tested.

II

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

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