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AD6650/PCB Datasheet(PDF) 1 Page - Analog Devices |
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AD6650/PCB Datasheet(HTML) 1 Page - Analog Devices |
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1 / 45 page  AD6650 Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver AD6650 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. FEATURES 116 dB dynamic range Digital VGA I/Q demodulators Active low-pass filters Dual wideband ADC Programmable decimation and channel filters VCO and phase-locked loop circuitry Serial data output ports Intermediate frequencies of 70 MHz to 260 MHz 10 dB noise figure +43 dBm input IP2 at 70 MHz IF −9.5 dBm input IP3 at 70 MHz IF 3.3 V I/O and CMOS core Microprocessor interface JTAG boundary scan APPLICATIONS PHS or GSM/EDGE single carrier, diversity receivers Microcell and picocell systems Wireless local loop Smart antenna systems Software radios In-building wireless telephony PRODUCT DESCRIPTION The AD6650 is a diversity intermediate frequency-to-baseband (IF-to-baseband) receiver for GSM/EDGE. This narrow-band receiver consists of an integrated DVGA, IF-to-baseband I/Q demodulators, low-pass filtering, and a dual wideband ADC. The chip can accommodate IF input from 70 MHz to 260 MHz. The receiver architecture is designed such that only one external surface acoustic wave (SAW) filter for main and one for diversity are required in the entire receive signal path to meet GSM/EDGE blocking requirements. Digital decimation and filtering circuitry provided on-chip remove unwanted signals and noise outside the channel of interest. Programmable RAM coefficient filters allow antialiasing, matched filtering, and static equalization functions to be combined in a single cost-effective filter. The output of the channel filters is provided to the user via serial output I/Q data streams. FUNCTIONAL BLOCK DIAGRAM PROG. FIR (RCF) 4TH ORDER CIC 7TH ORDER IIR LP FILTER AGC RELIN CTRL COARSE DCC REF /4 JTAG PLL/ VCO SERIAL PORT MUX LPF TWEAK GAIN I Q 0 90 12-BIT ADC DAC FINE DCC BIST SCLK SDFS SDO0 SDO1 DR LPF PROG. FIR (RCF) 4TH ORDER CIC 7TH ORDER IIR COARSE DCC MUX LPF Q I 12-BIT ADC FINE DCC BIST LP FILTER AGC RELIN CTRL TWEAK GAIN LPF VGA VGA AIN AIN BIN BIN CPOUT VLDO LF DAC MICRO CLK DIVIDER AD6650 GSM/ EDGE IF RECEIVER Figure 1. |
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